Greater amounts of RF and analog/mixed-signal circuitry are wending their way into SoC designs, often producing headaches for designers on a number of levels. First off, analog is just plain hard to do well. It's a time-consuming process fraught with detail and concern over performance. And on the back end, the analog portion of SoCs is most likely to cause yield problems.
A new tool from ChipMD enters the fray prior to layout in an effort to alleviate the yield issues. DesignMD, the startup's first offering, allows design to be approached with maximum yield as a primary goal rather than an afterthought. It automates what has been largely a manual process and does so while fitting cleanly into existing design flows. DesignMD performs transistor-level circuit optimization prior to layout using real manufacturing data from the foundry, tangibly bridging the gap between design and yield.
Performance and yield demands for analog circuits are almost incomprehensibly complex, yet these optimizations are typically done by hand today. In digital processes, yield optimization is often limited to transistor threshold voltages and temperature. Nanometer processes might have threshold voltage variations with a nominal distribution of 0.65 V and range from 0.5 V at the low end to 0.7 V at the high end. So individual transistors might vary within that range across a given die, and certainly across a wafer. If a high parametric yield is what you're looking for (and you should be), your circuit must be able to function with threshold voltages anywhere in that range.
Optimizing only for threshold voltage is difficult enough. In the real world, though, analog designers must optimize for a large number of parameters, including junction capacitance, N-substrate parameters, gain, gain bandwidth, slew, phase, power-supply rejection ratio, and more. According to Ravi Ravikumar, ChipMD's vice president of business development, the number of parameters being optimized for can be daunting. "One prospective customer told us they simulate for 32 corners for analog. They run from 300 to 500 simulations for each of those corners," says Ravikumar.
Why must one optimize for so many parameters? A typical plot of process variations addresses this question (Fig. 1). If you were optimizing only for the curve at the top right, Gain0, then the green ovals would represent the three-sigma conditions. Also, the point at center is the nominal operating point for that process. You'd center your design around that point and would have three-sigma operation as well as yield of up to 97%. Note, however, that one point falls to the right of the Gain0 curve, representing a yield failure.
What happens when you need to optimize for more than one parameter? Adding the gain-bandwidth (GBW) curve costs you a significant chunk of your operating range. Adding slew costs more, and phase costs even more—and that's only four parameters.
DesignMD is brought to bear in this process after defining topologies and design constraints, but before layout and parasitic extraction (Fig. 2). Inputs to the tool include a Spice netlist, process variation data sets, and a set of device models. The process variation data is the key to the tool's ability to size and optimize the design at the transistor level. That's so it will function across the entire set of process variations as well as the full range of operational conditions.
The tool's deterministic optimization engine (DOE) modifies the device sizes in the Spice netlist so that yield and performance are optimized across all process variations. The DOE's output is another Spice netlist with the same connectivity as the netlist that it received, but with the device sizes changed. It optimizes yield and performance through a series of Spice simulations, during which it determines the best device sizes across the entire range of process and operating-condition variations.
"The beauty of the deterministic engine is that it allows you to determine the level of optimization that needs to be done," says Ravikumar. "Then you do the final statistical analysis to prove that it was the right approach."
The tool will quickly arrive at a solution. Because of its deterministic nature, it drastically reduces the number of simulation runs that would otherwise be required to achieve similar results using traditional Monte Carlo analysis techniques.
By examining the results of these simulations, which are performed with the Spice simulator of the user's choice, the DOE can determine the sensitivities of the yield and performance to changes in device sizes and process parameters. Further simulations are run using these sensitivities. These additional simulations vary the device sizes, working toward a maximum increase in yield and performance. Once maximums are achieved, simulations are stopped and the results are reported to the user.
DesignMD uses what's termed as extended Monte Carlo analysis to deliver various views of the design and how it might best be optimized. The extensions to traditional Monte Carlo analysis are where the process-variation data comes in. Analysis performed by the tool includes sensitivity analysis, which shows how a given parameter might vary with changes to the design. For example, when looking at gain, the analysis might show that changing the width of a given transistor increases gain, but altering the width of another decreases it. The screen displays a list of parameters, each of which can be analyzed for sensitivity.
Another analysis capability is tolerance diagnosis, a more interactive form of analysis that gets to the heart of the matter for yield optimization. All performance parameters are listed in one portion of the screen, while in another, the user can interactively change one and instantly see the impact that change makes on all other parameters. So while the sensitivity analysis shows effects of changes on individual parameters, tolerance diagnosis shows the global impact of changes.
Beyond analyzing the design for transistor sizing, DesignMD will also provide some layout directives. For example, it can aid with portions of the design where the circuit can't tolerate transistor mismatches. "Analog designers know which transistors have to be matched, but when design is being done by one person or team with layout done by another, that's where communication can break down and DesignMD can help," says Ravikumar.
What overall impact does DesignMD make on yield? According to return-on-investment calculations done by early beta user Infineon, it is potentially substantial. With a company-wide yield improvement of just 5%, Infineon projects a potential annual savings of 300 million Euros by 2005. Further, the company expects a company-wide reduction in time-to-market of 5%, cutting another 300 million Euros. A 20% reduction in development efforts is seen as worth 14 million Euros, while a 50% reduction in risk of redesign buys another 30 million Euros. The total savings that Infineon projects by 2005 through the use of DesignMD is 644 million Euros ($736.5 million U.S.).
DesignMD is well integrated with Cadence's Spectre simulation environment and is interoperable with many Spice engines, both commercial and proprietary. Pricing for DesignMD starts at $50,000 for a one-year time-based license. It's available now.ChipMDwww.chipmd.com; (408) 725-9580