Desktop RTL Timing-Analysis Tool Tackles Timing Issues Early

Sept. 15, 2003
Achieving timing closure in system-on-a-chip designs in a reasonable amount of time can be daunting. You can wait until you get to the block-level integration stage, but you'll probably have an easier time of it if the RTL designers of each block...

Achieving timing closure in system-on-a-chip designs in a reasonable amount of time can be daunting. You can wait until you get to the block-level integration stage, but you'll probably have an easier time of it if the RTL designers of each block ironed out the timing issues. That's the idea behind InTime's Time Director, a tool that brings RTL timing analysis to the designer's desktop.

Time Director captures design intent at the block level as the RTL is being coded up. Static timing analysis is moved to the front of the design process, where it operates at RTL rather than waiting for a gate-level design representation. What results are easy edits of problem RTL and a quicker path to timing closure at both block and full-chip level.

With Time Director comes a full debug environment built around RTL timing, RTL schematics, and full hierarchy analysis combined with cross probing. It also provides block-level area estimates to help the design team plan for downstream packaging, data-flow, and floorplanning issues.

The tool easily integrates with existing synthesis and silicon virtual prototyping flows from Cadence, Magma, and Synopsys. It offers interfaces for standard outputs such as Synopsys-compatible constraints, LEF, DEF, and .lib.

Now in customer beta test, Time Director will ship this month. An annual time-based license costs $50,000.

InTime Softwarewww.intimesw.com (408) 565-0111

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.

Sponsored Recommendations

Comments

To join the conversation, and become an exclusive member of Electronic Design, create an account today!