With the lofty goal of creating a new level of design abstraction, Cadence Design Systems and CoWare will jointly pursue an electronic-system-level (ESL) design methodology. The vendors' strategic alliance is intended to mend the methodology rift between the transaction level represented by SystemC and the implementation level (RTL) by sharing verification, models, and standards. The glue between the two worlds, as the pair sees it, is the transaction level of abstraction that SystemC brings.
The alliance spans a joint licensing and cross-development agreement as well as coordinated marketing and standards strategies. As part of the alliance, Cadence will license and transfer its Signal Processing Worksystem (SPW) group to CoWare. That aspect of the agreement adds algorithm design to CoWare's processor, bus, system-on-a-chip (SoC) architecture, and hardware/software co-design tools. In addition, Cadence is making an equity investment in CoWare.
The two vendors have pledged a joint commitment to the SystemC standard, planning to unify emerging technologies by sharing technology and models. The first step in forging a new methodology is creating a system-to-silicon design flow. The flow would be based on CoWare's ConvergenSC and LISATek system-level design suites and the Cadence Incisive functional verification platform. Cadence and CoWare will work with vendors such as ARM to ensure that the unified ESL flow is supported by interoperable IP.
For details, go to www.cadence.com or www.coware.com.
