The need for verification has become a driving force behind the resurgence of electronic-system-level (ESL) development tools. Previously, ESL tools claimed to enable accurate chip design above the register-transfer level (RTL). Today, however, engineers need tools that provide system-level-verification capabilities.
Although everyone agrees on the importance of ESL design and verification, few agree on its definition. This disparity is hardly surprising. After all, few can even agree on the definition of a "system." It's little wonder that there are so many viewpoints on the definition of verification.
To get a sense of these different perspectives, let's consider three companies that represent a cross-section of ESL verification tools: Axis, CoWare, and Vast. This list is by no means complete. It merely serves to show the variance of ESL verification tools. Such tools span from hardware-level RTL and SystemC software simulation to high-level-algorithm architectural verification.
Starting at the RTL, take a look at Axis Systems, Inc. (www.axissystems.com). This company offers high-performance verification systems for the hardware and software development of complex systems-on-a-chip (SoCs). Several EDA vendors offer hardware and software co-verification solutions. But most of them rely on time-consuming, software-only, hardware-description-language (HDL) simulation. By contrast, Axis Systems offers a combined acceleration and emulation solution for co-verification.
This company defines ESL as concurrent hardware-software design and verification. Its accelerated simulation and hardware-emulation tool suites attempt to move emulation to an earlier point in the design cycle. With these tools, users can transition compiled or accelerated simulation into an in-circuit emulator. To debug a design within their simulation environment, they can switch from emulation to simulation.
Moving up to the next abstraction layer, we find CoWare, Inc. (www.coware.com). By supporting the SystemC hardware-software language, this company's tool suites provide architectural design, simulation, and analysis capabilities. Because today's chips are so complex, the RTL simulation of performance and power designs is often too slow and costly to be effective. CoWare's tools allow the user to create a transactional prototype model. This prototype provides event-accurate models for processors, buses, memories, and logic and software. It also enables designers to make architectural decisions, such as hardware-software partitioning, processor choice, coprocessor design, and bus characteristics. It can be refined to the register-transfer level for implementation. Unfortunately, an automated tool to VHDL or Verilog isn't yet available.
Lastly, let's check out a tool from the highest architectural-level point of view. Here, system behavior is captured algorithmically. It's then used to create a platform from which hardware and software partitions can be assigned. Vast Systems Technology (www.vastsystems.com) is one company that offers tools to create such a virtual platform.
This platform allows embedded designers to develop software long before silicon hardware is available. Basically, it serves as a model of the hardware-software system. The platform promises to execute embedded software while maintaining cycle accuracy. Once a platform is created, Vast's tools can be utilized to develop, edit, compile, and debug embedded software running on the platform.
The company claims to provide cycle-accurate simulation on processor models that run up to 250 times faster than other models. The models are even said to run faster than those generated from architectural descriptions. Vast's tool suites compete head-on against hardware systems that are meant to augment embedded software development, such as emulation and FPGA-prototype tools.
In summary, several existing electronic-system-level tools provide verification at each major level of system abstraction. Axis provides cycle-accurate, hardware-description-compilation capabilities that are critical for RTL emulation. Further up the "systems" ladder, CoWare enables SystemC software-compile, event-driven capabilities that are essential for both hardware and software simulation. At the highest level of abstraction, Vast provides the architectural level (pre-hardware-software) compilation of system algorithms.
All of these tools provide needed verification capabilities—albeit at different levels of abstraction. The only thing missing is a completely integrated tool suite that covers the entire verification space. Please share your thoughts with me. I can be reached at [email protected].