One of the better bets for enhanced verification productivity these days is adoption of an assertion-based methodology. Version 6.0 of Mentor's ModelSim fully supports a standards-based approach to assertion-based verification and coverage-driven flows. The simulator can handle Verilog 2001, VHDL, PSL, SystemC, and SystemVerilog.
Now offering a native assertion engine as well as assertion debugging, ModelSim 6.0 gives designers various ways to more easily ensure that designs match their functional specification. Also included are functional coverage capabilities, enabling users to track verification effectiveness. The combination of assertions and functional coverage produces coverage-driven verification. Here, designers use feedback from testing to target subsequent testing for greater productivity and effectiveness.
"We see people trying to achieve verification closure by using random-directed testbenches," says Robert Hum, VP and general manager of Mentor's Design, Verification and Test Division. "The question is how you direct those tests. Most use those testbenches to monitor embedded assertions and create vectors to address them. The point is to minimize the number of cycles to achieve the desired coverage."
The built-in assertion engine currently supports PSL, with SystemVerilog Assertions coming in revision 6.1. There's also testbench support for the SystemC verification library and several testbench constructs from the SystemVerilog 3.1a specifications.
Future revisions will integrate technology gained from Mentor's acquisition of 0-In Design Automation earlier this year. Mentor continues to market and support 0-In's assertion-based verification tools as is, with those tools being neutral to the simulator they're used with. But at some point, Mentor will integrate 0-In tools' formal and dynamic search capabilities to find difficult corner cases. This will be done by building a native interface to ModelSim.
ModelSim pricing starts at $4900. The tool is available immediately.
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