Equivalence Checker Handles Sequential Logic

For electronic system-level (ESL) methodologies to come to fruition, designers need to be able to nimbly move between levels of abstraction, especially when it comes to sequential logic. Design is done on a continuum that ranges from transactional-level models to fully timed RTL representations. But there's been a lag in tools that enable verification between levels of abstraction.

The SLEC product family from Calypto Design Systems addresses this lag. Touted as the industry's only sequential-logic equivalence checker, the SLEC platform enables design teams to quickly verify that RTL implementations match system-level specifications.

SLEC can prove functional equivalence between two IC designs that contain differences in level of abstraction and sequential behavior. It also can verify designs with sequential differences such as microarchitectural changes, state-machine modifications, timing rebalancing, and interface differences.

The SLEC sequential equivalence checking software is based on a patented hybrid verification technology that, unlike traditional combinational equivalence checkers, supports designs with sequential differences.

There are two initial products in the family: SLEC System and SLEC RTL. Design teams can use SLEC System to check that RTL implementations match a system-level design. SLEC RTL checks functional equivalence between two versions of an RTL design that have differences in architecture and timing.

The SLEC products are available now with support for Verilog, VHDL, SystemC, and C/C++ hardware descriptions. Pricing begins at $175,000 for a one-year license on Linux platforms.