As early adopters of 90- and 65-nm processes have learned, there's a big difference between what you design at these nodes and what gets printed on the wafer. The fact that these microscopic structures are being patterned on silicon with, at best, a 193-nm stepper has led to what's called the "lithography gap." And that gap grows wider with each new process generation. It behooves designers, then, to arm themselves with as much information about the process they plan to use as possible. To that end, Sigma-C has launched its Solid+. This lithography simulation and image-verification tool enables successful transfer of IC designs onto wafers to help prevent mask failures at 65 nm and below.
The "lithography gap" means that designs simply don't transfer onto the chip as drawn, which results in a high likelihood of respins. The key to avoiding poor yields is fast and accurate simulation of lithography results over a larger area. Solid+ accurately simulates areas up to 200 times larger than previously possible with traditional lithography simulation without compromising the accuracy of the results.
It uses faster algorithms and 3D capabilities to instantly identify hot spots during the design of a chip or a standard cell. It does so with full accuracy at the resist level for cells larger than 20 by 20 µm, letting designers know if their patterns at smaller process nodes can be accurately reproduced by a photolithography process.
Solid+ can help manufacturers maximize their current-generation exposure tools. It also can improve time-to-market through early definition and/or verification of lithography strategies. It already has been integrated into Toshiba's advanced lithography verification environment, where it's being used to help predict how design changes impact yields at smaller geometries.
Available now, Solid+ is priced from $140,000.
Sigma-C Software AG
www.sigma-c.com
