Methodology Kit Demystifies Wireless Design

Jan. 19, 2006
Many challenges are inherent in designing RF transceiver chips. Some of these challenges can cause long, sleepless nights for designers insufficiently versed in analog black magic. These include, but aren't limited to, system-level considerations

Many challenges are inherent in designing RF transceiver chips. Some of these challenges can cause long, sleepless nights for designers insufficiently versed in analog black magic. These include, but aren't limited to, system-level considerations, verification issues, dealing with parasitic extraction, and synthesis of inductors as well as modeling of passives.

Cadence's RF Design Methodology Kit represents an effort to help designers of wireless ICs shorten their cycle by better ensuring that silicon performance is aligned with design intent. The kit leverages various technologies that achieve intelligent management of parasitic extraction. It puts IC design within a system-level context through application of concurrent top-down and bottom-up design processes.

The kit includes an 802.11b/g wireless local-area network transceiver reference design, a full suite of RF verification IP, test plans, and applicability training on the RF design and analysis methodologies. It focuses on front-to-back RF IC design and addresses behavioral modeling, circuit simulation, layout, extraction and resimulation, and inductor synthesis. It also addresses IC verification within a system context.

Links to system-level environments are now offered through Cadence's Virtuoso AMS Designer, a custom mixed-signal design platform that provides links to the Mathworks' Matlab and Simulink. The result is an executable specification that designers can use throughout the design process as a "golden reference" of functionality.

Contact Cadence Design Systems directly to obtain information about availability and pricing.

Cadence Design Systems
www.cadence.com/products/kits/

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