Two pressing issues loom for chip designers—the length of time it takes to achieve design closure and the difficulties in attaining acceptable fab yields. With what Cadence terms "manufacturing-aware" chip optimization, Chip Optimizer addresses both issues with a tool that eliminates oversimplified interconnect and process models.
Chip Optimizer models, analyzes, and optimizes the true shapes represented in the physical design as well as the spaces between them. By doing so, it can optimize for manufacturability, yield, and performance simultaneously. For example, the tool can manage wire widths and spacing to optimize coupling capacitance as well as yield issues. It also manages the use of vias so they're located intelligently and judiciously.
In performing its optimizations, Chip Optimizer represents an evolution of earlier state-space exploration tools, taking a 3D view of the design. Shapes and spaces can be positioned in the exact configuration and location required to correct sub-wavelength, spacing, and topological effects.
The tool operates in both the digital and semi-custom design spheres. Falling between place-and-route and signoff, Chip Optimizer's approach to digital designs optimizes them for manufacturing (see the figure). The goal is to avoid post-GDSII processing wherever possible so designers don't lose control of the result. In the semi-custom realm, Chip Optimizer is used primarily in the design of on-chip interconnects.
The tool is a native application developed on the industry-standard OpenAccess design database and interface. It supports Cadence's design platforms as well as third-party flows.
Chip Optimizer is available now. Pricing depends on configuration.
Cadence Design Systems
www.cadence.com
