Many of the bottlenecks in complex system-on-a-chip (SoC) design projects aren't really related to design itself, but rather to the design process. Factors such as multisite development work, staffing issues, and the quality of libraries and third-party IP aren't quite up there with timing closure, but they're quietly becoming problematic.
Synopsys' Professional Services organization has put together what it hopes is an answer to these design-process issues in the Pilot Design Environment. Based on the established Galaxy and Discovery design and verification platforms, the Pilot environment is a complete RTL-to-GDSII flow with built-in methodologies and utilities to improve designer productivity.
A package of utilities within the Pilot flow addresses the problem of commonly missing and/or inaccurate design data. Some of these utilities qualify and correct incoming RTL and libraries, while others generate a complete and clean set of technology files.
Meanwhile, real-time metrics are applied throughout the flow to report progress and provide visibility into when design closure might be expected. These metrics also allow measurement of productivity gains.
The flow's structured environment enables data coherency in multisite development situations. Design and project data are kept separate, which facilitates multiproject use and simplifies the retargeting of designs to new libraries and processes. The flow supports popular revision-control software tools.
Pilot's pricing varies with customization. Support costs $75,000 per year. It's available now on a limited basis.
Synopsys
www.synopsys.com
