Packaging Analyzer Targets SiPs, CSPs, And Stacked Packages

Jan. 22, 2007
Ansoft's latest Turbo Package Analyzer (v5) provides new automation, design flow, and simulation capabilities needed for the extraction of the electrical characteristics of complex ball-grid array (BGA)-style packaging.

The latest version of Turbo Package Analyzer (TPA v5) introduces new automation, design flow, and simulation capabilities needed for the extraction of the electrical characteristics of complex ball-grid array (BGA)-style packaging, including wire-bond (WBBGA), flip-chip (FCBGA), chip-scale packages (CSPs) and System in Packages (SiP).

TPA v5 increases the capacity of the solver to address larger-sized packaging problems and introduces greater automation for generating and/or modifying 3D package layouts. TPA v5 introduces a new user interface that includes new 2D editing and 3D viewing capabilities, unlimited undo/redo capability, and powerful new editing and automation features, such as geometry validation checking and support for VB scripting.

Combined with AnsoftLinks, a tool for simplifying data import and export between EDA and CAD packages, TPA v5 generates resistance, inductance and capacitance (RLC) models directly from popular package design tools. It accepts CAD data and fully characterizes the entire package in three dimensions. Extracted sub-circuits can be exported into Nexxim, Ansoft's circuit simulation software, or existing SPICE tools (SPICE/IBIS format) for subsequent transient analyses, such as crosstalk, overshoot and time-domain reflectrometry.

TPA v5 highlights include:

  • AC RLC computation for 3D structures
  • Automated coupled full-package AC RLC extraction using efficient surface triangulation algorithms
  • DC resistance computation for 3D structures
  • Automated net-by-net full-package dc resistance extraction using a volumetric (tetrahedral) mesh
  • Ability to designate source and sink terminal assignment on any given net
  • New 2D layout editor and 3D viewer
  • Create advanced wire-bond or flip-chip designs from scratch or modify/correct designs imported from third-party layout tools
  • System-in-Package (SiP) design with multiple wire-bond configurations including Trace-to-trace, Die-to-die and Cascaded
  • User-defined wire-bond profiles expanding shapes from JEDEC 4- and 5-point to include arbitrary polylines
  • Complex solderball models capture true shape and subsequent electrical performance of solderballs and flip-chip solder-bumps
  • New layer stack-up editor
  • New via pad stack editor
  • VB scripting support
  • Validation check to verify setup, including detection of self-intersecting polygons; disjoint nets; overlapping (dc-shorted) nets, vias and bond wires; illegal connections between bonding pads and bond wires
  • Microsoft Windows XP Professional x64 support

TPA v5 is available for Microsoft Windows XP Professional, Windows XP x64 Edition and Windows Server 2003. Contact your nearest Ansoft sales office for pricing information. To download a high-resolution TPA v5 image, go to Ansoft's FTP site.

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