Accelerator/Emulators Speed Verification And Debugging

May 24, 2007

There's really no getting around it. The complexity of today's chip designs will eventually force you to adopt hardware-assisted verification in some form. Software simulation alone is too slow. Meanwhile, functional verification remains Public Enem

David Maliniak

Mentor Graphics, which has a long history in the hardware-assisted verification arena, has made its latest splash with the Veloce family of systems. Available in three initial configurations, the Veloce simulation accelerators and/or in-circuit emulators (ICEs) combine the fast runtime speeds and model accuracy of FPGA-based hardware-assisted verification systems with the simulation-like debug and very fast compilation of systems based on custom ASICs.

The heart of the Veloce systems' hardware architecture is a custom ASIC built on a 90-nm process. The chip includes 500 kbits of dual data-rate trace memory as well as a built-in debug engine. According to the company, this results in simulation-like debugging during acceleration as well as during ICE, with visibility into every RTL signal during the entire duration of the test. A trace-compression engine also built into the ASIC provides efficient transport of debug data from the Veloce system to a workstation or PC for analysis.

For design-team-level acceleration and emulation, the Veloce Trio-24/48 and Veloce Solo systems accommodate three users and one user, respectively, with systems intended for use in data centers. Veloce Solo is a personal system that can sit under a designer's desk (see the table). Veloce Quattro is an enterprise-class system for large designs. Shared by up to four users, it's intended as a lab unit.

A standout specification for the Veloce family is runtime speed. As an accelerator, the systems run at over 1 MHz. As ICEs, they've been clocked at up to 1.5 MHz. That translates into faster turnaround times and can mean the ability to compile a design multiple times in a single day.

The Veloce hardware-assisted verification systems are available now. Contact Mentor Graphics directly for pricing.

Mentor Graphics
www.mentor.com

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.