A statistical static-timing analysis (SSTA) methodology is now available from Magma Design Automation for UMC’s 90- and 65-nm processes. Based on Magma's Quartz SSTA tool, the methodology addresses timing and yield problems caused by process variation in 65-nm and below technologies. The methodology, which includes statistical library support, extraction for interconnect variation, and statistical analysis, has passed UMC's qualification process.
Traditional static-timing analysis (STA) approaches don’t scale to the 65-nm node. STA, which relies on brute-force corner and highly guard-banded on-chip variation (OCV) analysis, and derives timing based on pessimistic and worst-case gate and interconnect models, can be overly conservative and inaccurate. It’s also unable to account for process and metal variations, causing designers to sign off on designs that may ultimately fail in silicon. This unreliable approach results in lower performance and longer, more costly design cycles.
Quartz SSTA supplements traditional sign-off methods with powerful and accurate statistical static-timing analysis. It uses random variables rather than fixed delays and produces a statistical distribution, rather than best-case and worst-case models.
This approach can account for global (inter-die) and random (intra-cell) process variations, composite-current-source (CCS) models, statistical leakage analysis, and statistical optimization, automatically identifying clocks, paths, cells, and metal layers that are sensitive to variation. Utilizing the unified data model architecture, Quartz SSTA then works with Magma's IC implementation system to automatically fix timing problems that result from variation. With this process-variability-aware IC implementation flow, pessimism is eliminated, predictability is enhanced, and timing closure and sign-off can be achieved faster and easier.
Magma Design Automation
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