Manufacturability is paramount as
IC designers move to process
nodes below 90 nm. It's bad
enough that tool runtimes are significantly
longer and timing closure becomes
much more challenging. But then designbased
yield limiters, or "gotchas," sap performance
and cause yields to plummet.
Tied directly to the chip layout itself, these
profit killers must be designed out from
the start and can't be fixed in the fab.
Yet a new generation of routing technology
will bring manufacturing awareness
to the routing stage of the cycle. For
example, Pyxis Technology's NexusRoute
is a DFM-aware, yield-driven auto router
that comprehends and optimizes manufacturability
and yield concurrently with
the actual routing and timing closure
process. Intended for process technologies
of 65 nm and below, it reduces design closure and manufacturing cycle
time and increases chip yield by up to
10%, according to Pyxis.
At 45 nm, existing routing architectures
will struggle to handle the complex interactions
between design and process.
NexusRoute, which can be easily integrated
into existing design flows using open
industry-standard interfaces, scales with
the newer technologies (providing up to
4X gains in design and manufacturing closure
time). The tool simultaneously optimizes
design for timing, manufacturability,
and yield as well (see the figure).
The company also has rolled out Pyxis
Professional Services, a set of consulting
and methodology services to help
designers improve the yield on design
blocks while assessing the impact of
DFM design practices within their design
environments. NexusRoute and Pyxis
Professional Services
are available
now. NexusRoute
pricing starts at
$400,000 for a oneyear
time-based
license.
Pyxis Technology
www.pyxistech.com
