As IC design sizes continue to double
every 18 to 24 months, those
charged with testing the finished
product are challenged on multiple fronts.
Test-data volume and testing time are
expanding, while manufacturing throughput
is reduced. The International Technology
Roadmap for Semiconductors (ITRS)
predicts that by 2008 the industry will
need 200 times more test-data volume
compression, with the requirement growing
exponentially over the next five years.
In the latest iteration of its TestKompress
automatic test-pattern generation
(ATPG) tool, Mentor Graphics' Xpress
technology ups the compression ante
from 80 to 90 times previous versions to
well over 100 times. Additionally, the tool
uses new compression algorithms that
enable it to achieve the same test quality
with fewer patterns.
Historically, logic built-in self-test
(BIST) schemes have struggled with
handling unknown states in the design
(referred to as X states). X states, of
which there can be many in uninitialized
memory, confound tests because they're
unknown logic values. They're traditionally
dealt with through the addition of
additional so-called "top-up" test patterns
that bypass compression circuitry.
Mentor's X-masking technology adds
selection logic before the X compaction
stage, enabling test engineers to decide
which paths to observe. Furthermore, a
new Xpress compactor enhances the
ability to examine faults in the presence
of X states (see the figure).
With the ITRS data in mind, Mentor's
roadmap for test compression encompasses
developmental technology that
allows higher levels of compression without
the need for changes in the scan
architecture. It essentially involves a cascade
of compactors.
TestKompress Xpress is available for
beta evaluation and will be in production
in the fourth quarter release of TestKompress,
scheduled to ship in November.
Mentor Graphics
www.mentor.com
