Collaboration Provides Sub 65-nm Variation-Aware IC Design Flows
This week at the Design Automation Conference (DAC), Extreme DA and semiconductor foundry UMC announced their collaboration on variation-aware IC design flows for 65-nm and finer process technologies. Extreme DA specializes in IC performance and yield-imp
This week at the Design Automation Conference (DAC), Extreme DA and semiconductor foundry UMC announced their collaboration on variation-aware IC design flows for 65-nm and finer process technologies. Extreme DA specializes in IC performance and yield-improvement software. The jointly-developed design flows reduce uncertainty and predict performance and yield by analyzing timing behavior in the presence of process variations.
The first flow, based on extreme DA's Extreme Gold statistical analysis suite, has already been applied to a test chip at UMC’s 65-nm process node. The collaborative efforts are in the following areas:
Characterization of UMC libraries for global and mismatch variations to analyze these effects
Location-based on-chip variation (LOCV) model construction for improved accuracy of variation analysis
Variation-aware extraction and timing analysis on a 65-nm test chip
The Extreme Gold sign-off suite is a variation-aware performance and yield analysis flow for 65- and 45-nm ICs. The suite models IC variations and analyzes the statistical effects on extraction, timing, and noise using the GoldTime timing analyzer.
