A highly integrated SONET/SDH overhead processor (OHP) and termination device for OC-3, -12 and -48 applications, the Explorer chip combines standard overhead termination functionality with ITU-T jitter-compliant clock and data recovery and clock synthesis, automatic protection switching, packet over SONET, OC-3 digital cross connection, and direct access to the VC-3/4 frames. The device can be configured to provide complete physical layer and overhead termination for quad independent OC-3s, 4xOC-3c and OC-12c. And it can be seamlessly integrated with the firm's SST-48 family to form a complete OC-48 termination solution. Explorer multi-rate device allows for SDH/SONET and ATM/POS interfaces ranging from 51 Mbps to 2.4 Gbps. Parallel and serial SDH/SONET interfaces are provided and comply with ITU-T, ANSI and Bellcore requirements for jitter generation and jitter tolerance at STS-1 to STS-12 rates over the industrial temperature range. The ATM interfaces are compliant to the ATM Forum's UTOPIA standard, supporting either two 8-bit UTOPIA Level 1 interfaces or one 16-bit UTOPIA Level 2 interface.
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