In its latest release, TestBencher Pro v7.0 now supports cycle-based bus transactions. The application provides designers with a graphical environment for generating cycle-based or time-based, bus-functional models from language independent timing diagrams. Features include automatic port and signal extraction from HDL models, parameterization of both state and timing values through function-call parameters or data files, checkers for signal stability and/or edge transitions within a window of time, and conditional application of edge transitions based on these checks. Available for Solaris/HP-UX and Windows NT, prices start at $9,500.