“Today he’s gonna make it to the top
And be the Chip Synthesis Hero, silicon in his sight
He took one mega design, placed the gates, cut the time
Chip Synthesis Hero, he got it right.”
This veteran chip jock has been at it for a long time and brings a world of silicon hurt to the table, especially when we’re talkin’ IC — that’s integrated circuits, for those in the know. He knows the drill and knows what works. He knows that the design flow needs to be improved and new tools are what make him the Chip Synthesis Hero and not just the average chip jock.
And what are those new tools? Oh yeah, we’re talkin’ ’bout chip synthesis tools. He’s made the switch from old-school synthesis to the new hot, hot, hot chip synthesis.
What, you wonder, is chip synthesis? Why, it’s the new electronic design automation (EDA) product category that re-imagines and re-creates logic synthesis. Think of it as the answer for physical register-transfer-level (RTL) synthesis for designs of 100 million gates or more. Tools in this category can synthesize RTL code to placed gates in a single pass and do so much faster than traditional synthesis flows. Our hero knows that these tools have a secret RTL placement approach that eliminates unending design closure and iterations between synthesis and layout.
You betcha! This is a fundamental shift in how synthesis is applied to chip design and implementation and the Chip Synthesis Hero saw it first.
How does he do it? He jams his RTL code into the software. The tool partitions the code into blocks, places it in the context of a floorplan and implements each block through to placement. Not to worry: Chip-level constraints are automatically propagated across the blocks and the design is optimized for the best possible quality of results. Perfect!
Better yet, during the optimization phase, our Chip Synthesis Hero found that the tool will repartition the design at the RTL and re-implement the code until chip-level constraints are met.
What does he think? It’s hotter than hot, he says. It’s the first tool ever to automate the manual process of checking results for design congestion and re-implementing it until it is correct. How’s that? He feeds the chip floorplan as input into chip synthesis or, if no floorplan exists, it will create a floorplan including macro, pin, and I/O placement. When finished, the tool produces a placed design and a netlist that meet constraints within the context of the desired floorplan. He concluded that chip synthesis gave him better results and in a fraction of the time than old-school synthesis.
“Gotta keep on designin’ to be the Chip Synthesis hero
Got silicon in his eyes, he took one chip design and came alive
Yep! He’s gotta keep on designin’, doesn’t want to be another zero…”
And, there you have it––an ode to the Chip Synthesis Hero who took one design, cut down the time, saving a dime and inspired a rhyme!