The Taiwan Semiconductor Manufacturing Company (TSMC) has made available several unified and interoperable electronic design automation (EDA) technology files for its 65nm, 40nm, and 28nm process nodes.
The design technology file suite includes an interoperable process design kit (iPDK), interoperable design-rule checking (iDRC), layout-versus-schematic checking (iLVS), and interoperable interconnect extraction (iRCX).
The iPDK, iDRC, iLVS, and iRCX technologies are developed and jointly validated with TSMC's EDA partners under the industry-wide Interoperability Project that is an integral part of the company's Open Innovation Platform (OIP).
Process and design rules for advanced semiconductor manufacturing technologies are more complex and require detailed, accurate descriptions for correct chip layout creation, simulation and post-layout verification and analysis. TSMC collaborates with major EDA ecosystem partners who are part of the OIP Interoperability Project to define and develop a unified architecture and interoperable formats based on TSMC process requirements. The company's EDA partners support the new format in their tools and qualify tool accuracy against actual silicon measurements. This qualification process eliminates data inconsistency, reduces tool evaluation time and improves design accuracy.
TSMC developed its first 40nm iDRC/iLVS in collaboration with development partners Mentor Graphics and Synopsys as well as QA/validation partners Magma Design Automation and Cadence Design Systems. TSMC also developed its first 65nm iPDK in collaboration with Synopsys and Ciranova as development partners in addition to QA/validation partners Magma and Springsoft. Both interoperable technology files have been under customer evaluation since July of last year. After extensive testing, the 65nm iPDK, the 40nm iPDK, and the 65nm and 40nm iDRC and iLVS technology files are now available for production designs.