Please read the sections “Important notice” and “Warnings” at the end of this document www.infineon.com 2026-09-18 PD-98045A RIC70115 - Rad hard high/low side gate driver for GaN HEMT and LL Si FET Features • Truly Differential Input (TDI) enhances immunity to input noise and enables both high and low side operation • Integrated linear regulator provides regulated optimal gate drive voltage for GaN HEMT and logic level (LL) Si FET while supporting wide bias voltage range • Short propagation delay enables high switching frequency • Integrated miller clamp improves robustness against undesired induced turn-on • Target radiation tolerance o High dose rate (50-300 rad(Si)/s) of 100 krad(Si), characterized to 150 krad(Si) o Characterized to have no sensitivity to enhanced low dose rate (ELDRS) at 10 mrad(Si)/s • Target Single event effect (SEE) hardness o No SEB or SEL up to LET of 83 MeV·cm2/mg o SET characterized up to LET of 83 MeV·cm2/mg • Planned to be electrically screened and qualified to MIL-PRF-38535, Class V Potential applications • Satellite Bus and Payload • Power Conditioning Unit • Power Distribution Unit • DC-DC Converter Ordering information Table 1 Ordering information Orderable part number Package type Device level Total ionizing dose level 5962R2420701VXA 16-pin LCC Level V1, 3 100 krad(Si) RIC70115G 16-pin LCC Engineering model 2 RIC70115EVAL1 Evaluation board 1 Per MIL-PRF-38535 2 Intended for engineering evaluation only, devices are only electrically tested at 25°C and for hermeticity 3 MIL-PRF-38535 QMLV certification pending Product summary • VDD = 17.1 V (abs max) • VDRV = 4.8 V • ISRC/SNK = 1.5 A / 2.5 A • TA = -55°C to 125°C 16 pin LCCVSS VDD LDO IN+ IN- SRC SNK VDRV COM CLAMP 4.8V SW VBUS VIN VBIAS Figure 1 Simplified schematic 2 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET Descriptioni Descriptioni RIC70115 is a radiation hardened gate driver. It is intended for harsh radiation environments such as space, with electrical parameters specified pre and post-irradiation up to 100 krad(Si) and single event effects (SEE) characterized up to a linear energy transfer (LET) of 83 MeV·cm2/mg. RIC70115 is available in a hermetically sealed 16 pin CLCC package and operates over the full military ambient temperature range of -55°C to 125°C. RIC70115 is intended for use with rad hard GaN Schottky Gate (SG) HEMT or rad hard logic level gate drive MOSFET. It features high gate drive strength of 1.5A/2.5A (source/sink) and fast propagation delay to enable high frequency, low loss switching. It integrates an optional LDO, which allows a wide bias supply to be used while providing an ideal and tightly regulated drive voltage, required by GaN HEMT devices. It additionally includes a miller clamp, which helps to prevent against induced turn on from high dv/dt on the drain-to-source of the power switch. RIC70115 features TDI logic, which improves robustness against noise on the input pins as well as enable support for high side operation.VDD RIC70115 IN+ IN- VSS VDRV SRC SNK CLAMP COM VDD RIC70115 IN+ IN- VSS VDRV SRC SNK CLAMP COM VIN VIN High voltage offset VDD SW +VCMR- VBUS Figure 2 Typical half bridge application block diagram 3 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET Table of contents Table of contents Features ........................................................................................................................................ 1 Potential applications ..................................................................................................................... 1 Ordering information ...................................................................................................................... 1 Descriptioni.................................................................................................................................... 2 Table of contents ............................................................................................................................ 4 1 Block diagram ........................................................................................................................ 5 2 Pin configuration and functionality .......................................................................................... 6 2.1 Pin configuration ..................................................................................................................................... 6 2.2 Pin functionality ...................................................................................................................................... 6 3 Electrical parameters.............................................................................................................. 7 3.1 Absolute maximum ratings ..................................................................................................................... 7 3.2 ESD ratings ............................................................................................................................................... 7 3.3 Thermal characteristics........................................................................................................................... 7 3.4 Recommended operating conditions ..................................................................................................... 8 3.5 Electrical characteristics ......................................................................................................................... 8 4 Timing Diagrams .................................................................................................................. 11 5 Typical Characteristics .......................................................................................................... 12 6 General description .............................................................................................................. 15 6.1 Radiation performance ......................................................................................................................... 15 6.1.1 Total ionizing dose (TID) .................................................................................................................. 15 6.1.2 Single event effects (SEE) ................................................................................................................. 15 6.2 Input power and bias............................................................................................................................. 15 6.2.1 Internal LDO...................................................................................................................................... 15 6.2.2 External bias ..................................................................................................................................... 15 6.2.3 Negative drive................................................................................................................................... 16 6.3 Input ....................................................................................................................................................... 16 6.3.1 Minimum input pulse ....................................................................................................................... 16 6.3.2 Selection of TDI input resistors ........................................................................................................ 17 6.3.3 Low side ............................................................................................................................................ 18 6.3.4 High side ........................................................................................................................................... 18 6.3.5 Optional additional input filter ........................................................................................................ 19 6.4 Output .................................................................................................................................................... 20 6.4.1 Miller clamp ...................................................................................................................................... 20 6.5 Fault protection ..................................................................................................................................... 20 7 Package details .................................................................................................................... 21 7.1 LCC ......................................................................................................................................................... 21 Revision history ............................................................................................................................ 22 Disclaimer .................................................................................................................................... 23 4 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET Block diagram 1 Block diagramVSS VDD OTP LDO IN+ IN- Diff. Amp + LPF Diff. Schmitt Trigger Comp. SRC SNK VDRV COM CLAMP CONFIG1 CONFIG2 CONFIG3 Input blanking time UVLO 4.5V/4.3V Miller clamp delay logic VDD 4.8V Figure 3 Block diagram 5 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET Pin configuration and functionality 2 Pin configuration and functionality 2.1 Pin configuration3 4 5 6 11 12 13 14 10987 1512 1 16 VDDCONFIG2 CONFIG3 VSS IN+ IN- NC CONFIG1 VSS COM COM CLAMP SNK SRC VDRV VDRV 16 pin LCC Figure 4 RIC70115 pin assignments (top view) 2.2 Pin functionality Table 2 Pin functionality Pin Symbol Description 1 VDD Bias power input for internal LDO 2 CONFIG2 Configuration pin. Pin has internal pull up resistor. Leave open or connect to VSS to program input blanking time 3 CONFIG3 Configuration pin. Pin has internal pull up resistor. Leave open or connect to VSS to program input blanking time 4, 9 VSS Return. Connect to ground. 5 IN+ Positive input 6 IN- Negative input 7 NC No connection. Leave pin disconnected (pin is internally electrically connected) 8 CONFIG1 Configuration pin. Pin has internal pull up resistor. Leave open or connect to VSS to program input blanking time 10, 11 COM Return for output drive stage. Connect to VSS for 0 V turn off or apply negative voltage for negative voltage turn off 12 CLAMP Miller clamp, connect to gate of GaN HEMT / Si FET 13 SNK Negative output of gate driver, sinks current 14 SRC Positive output of gate driver, sources current 15, 16 VDRV 4.8 V output of internal LDO, voltage used for drive. It is required to connect an external capacitor of at least 2 μF from VDRV to VSS. Bias power can be directly applied to this pin to bypass internal LDO. 6 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET Electrical parameters 3 Electrical parameters 3.1 Absolute maximum ratings Absolute maximum ratings indicate limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to VSS unless otherwise stated in the table. Table 3 Absolute maximum ratings Symbol Definition Min Max Units VDD VDD pin to COM -0.3 17.1 V VDD pin to VSS -0.3 17.1 V VDRV VDRV pin -0.3 6.5 V VIN IN+, IN- pins -6.5 0.3 V VOUT SRC, SNK and CLAMP pins to COM -5 V SRC, SNK and CLAMP pins to VSS -0.3 VDRV+0.3 V VCOM COM to VSS -5 0.3 V TJ Operating junction temperature -55 150 °C TS Storage temperature -65 150 °C TL Lead temp (soldering, 10s, 0.063 in (1.6 mm) from case) 300 °C 3.2 ESD ratings Table 4 ESD ratings Symbol Definition Value Units VESDHBM ESD Human Body Model (HBM)1, Class 3A per MIL-STD-883, Method 3015 4 kV VESDCDM ESD Charged device model (CDM)2 1 kV 1 Per ANSI/ESDA/ JEDEC JS-001 2 Per ANSI/ESDA/JEDEC JS-002 3.3 Thermal characteristics All ratings are specified under board mounted and still air conditions. Table 5 Thermal characteristics Symbol Definition Min Typ Max Units RΘJC Thermal resistance, junction to case 23.1 °C/W RΘPWB Thermal resistance, junction to board 34.7 °C/W RΘJA Thermal resistance, junction to ambient 50.4 °C/W 7 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET Electrical parameters 3.4 Recommended operating conditions For proper operation the device should be used within the recommended operating conditions. All voltage parameters are absolute voltages referenced to VSS unless otherwise stated. Table 6 Recommended operating conditions Symbol Definition Min Max Units VDD VDD bias voltage to COM 4.75 15 V VDD bias voltage to VSS 4.75 13.2 V VDRV External voltage on VDRV pin (VDD=VDRV)1 4.75 5.25 V VCOM COM to VSS -3 0 V VCMRS Common mode voltage range (static DC)2 -150 10 V VCMRD Common mode voltage range (dynamic AC)2, 3 -200 10 V VCMSR Common mode voltage slew rate 100 V/ns TA Operating ambient temperature -55 125 °C 1 Connecting pins VDD and VDRV together will bypass internal LDO, allowing for drive voltage to be externally set 2 Measurement from input signal across resistors to IN+ and IN- pins, meaning negative voltage is positive voltage on switch node in half bridge 3 Duration of AC voltage transient event must be shorter than specified blanking time 3.5 Electrical characteristics VDD = 4.75 V to 13.2 V, COM = VSS = 0 V and TA = TJ = -55 to 125°C unless otherwise stated. All pins with respect to VSS unless otherwise stated. All parameter ratings apply over a total ionizing dose (TID) of 100 krad(Si) with exposure at a high dose rate (HDR) of 50-300 rad(Si)/s or at a low dose rate (ELDRS) of 10 mrad(Si)/s. Table 7 Electrical characteristics Symbol Definition Min Typ Max Units Test Conditions Input power IINQNL VDD operating current unloaded (500 kHz switching frequency) 2.4 3 mA VDD=4.75 V 2.4 3 mA VDD=13.2V IINQ VDD operating current loaded (500 kHz switching frequency) 5 6.5 8 mA VDD=4.75 V, CL=1.2 nF 5 6.5 8 mA VDD=13.2 V, CL=1.2 nF IINSD VDD standby current 1.5 2.1 2.8 mA VDD=4.75 V 1.5 2.1 2.8 mA VDD=13.2 V VDRVUVLO+ VDRV UVLO rising threshold 4.3 4.5 4.6 V VDRVUVLO- VDRV UVLO falling threshold 4.2 4.3 4.6 V VDRVHY VDRV UVLO hysteresis 150 mV VDDUVLO+ VDD UVLO rising threshold 4.45 4.6 4.7 V VDDUVLO- VDD UVLO falling threshold 4.35 4.5 4.6 V VDDVHY VDD UVLO hysteresis 100 mV 8 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET Electrical parameters Symbol Definition Min Typ Max Units Test Conditions VLDO Internal LDO dropout (VDD-VDRV) 93 mV VDD=4.75 V, IVDRV=30 mA ILDO VDRV current limit 160 220 300 mA VDD=13.2 V, VDRV=3V 120 206 290 mA VDD=4.9 V, VDRV=3 V VDRV VDRV regulation voltage 4.7 4.8 4.85 V VDD=4.9 V IVDRV =20 mA 4.7 4.8 4.85 V VDD = 5.2 V IVDRV =60 mA 4.7 4.8 4.85 V VDD=5.5 V IVDRV =100 mA Input logic VIHD Differential input logic threshold for turn on (low to high) 1.2 2.0 2.85 V 47 kΩ on IN+, IN- VCMR = 0 V VILD Differential input logic threshold for turn off (high to low) 0.9 1.3 2.2 V 47 kΩ on IN+, IN- VCMR = 0 V Output VOH Logic “1” output voltage (VDRV-SRC) 50 mV ISRC=20 mA VOL Logic “0” output voltage (SNK-COM) 50 mV ISNK=20 mA RSRC Output high internal resistance 1.4 2 Ω RSNK Output low internal resistance 0.7 1 Ω RCLAMP Miller clamp internal resistance 0.7 1 Ω ISRC Output high short circuit pulsed current1 1.5 A PW ≤ 10 μs ISNK Output low short circuit pulsed current1 2.5 A PW ≤ 10 μs ICLAMP Miller clamp current1 2.5 A VCLAMP Miller clamp voltage threshold 0.7 0.8 0.9 V Timing tr Rise time1 4 ns CL=1nF tf Fall time1 4 ns CL=1nF ton Turn-on propagation delay1 25 ns CL=1nF CONFIG3=OPEN CONFIG2=OPEN CONFIG1=OPEN toff Turn-off propagation delay 1 23 ns ΔtLHHL Propagation delay matching1 1.4 2.9 ns tPWmin Shortest input pulse transferred to the output1 12 ns ton Turn-on propagation delay1 45 ns CL=1nF CONFIG3=OPEN CONFIG2=OPEN CONFIG1=VSS toff Turn-off propagation delay1 44 ns ΔtLHHL Propagation delay matching1 0.9 1.9 ns tPWmin Shortest input pulse transferred to the output1 18.5 ns 9 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET Electrical parameters Symbol Definition Min Typ Max Units Test Conditions ton Turn-on propagation delay1 63 ns CL=1nF CONFIG3=OPEN CONFIG2=VSS CONFIG1=OPEN toff Turn-off propagation delay1 62 ns ΔtLHHL Propagation delay matching1 0.9 1.9 ns tPWmin Shortest input pulse transferred to the output1 36 ns ton Turn-on propagation delay1 83 ns CL=1nF CONFIG3=OPEN CONFIG2=VSS CONFIG1=VSS toff Turn-off propagation delay1 82 ns ΔtLHHL Propagation delay matching1 0.9 2.4 ns tPWmin Shortest input pulse transferred to the output1 54 ns ton Turn-on propagation delay1 102 ns CL=1nF CONFIG3=VSS CONFIG2=OPEN CONFIG1=OPEN toff Turn-off propagation delay1 102 ns ΔtLHHL Propagation delay matching1 0.9 2.4 ns tPWmin Shortest input pulse transferred to the output1 72 ns ton Turn-on propagation delay1 122 ns CL=1nF CONFIG3=VSS CONFIG2=OPEN CONFIG1=VSS toff Turn-off propagation delay1 121 ns ΔtLHHL Propagation delay matching1 0.8 1.8 ns tPWmin Shortest input pulse transferred to the output1 90 ns ton Turn-on propagation delay1 141 ns CL=1nF CONFIG3=VSS CONFIG2=VSS CONFIG1=OPEN toff Turn-off propagation delay1 140 ns ΔtLHHL Propagation delay matching1 0.8 2.2 ns tPWmin Shortest input pulse transferred to the output1 108 ns ton Turn-on propagation delay (maximum blanking) 1 160 ns CL=1nF CONFIG3=VSS CONFIG2= VSS CONFIG1= VSS toff Turn-off propagation delay (maximum blanking) 1 159 ns ΔtLHHL Propagation delay matching1 0.8 2.4 ns tPWmin Shortest input pulse transferred to the output1 126 ns Overtemperature protection OTP+ Internal overtemperature protection rising threshold1 174 178 185 °C OTP- Internal overtemperature protection falling threshold1 132 141 °C 1 Parameter not subject to production test. Parameter guaranteed by design and characterization. 10 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET Timing Diagrams 4 Timing Diagrams(IN+ - IN-) SRC SNK 10% 90% ton tr toff tf VOH VOL 50% ΔtLHHL=ton-toff Figure 5 Rise time, fall time, propagation delay and delay matching definition 11 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET Typical Characteristics 5 Typical Characteristics Figure 6 IINQL input current unloaded and IINQ input current with CL=1.2nF Figure 7 IINSD input standby current Figure 8 VDRV and VDD UVLO rising and falling thresholds 1.8 1.85 1.9 1.95 2 2.05 2.1 2.15 2.2 2.25 2.3 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) VDD=4.75V VDD=13.2V IINSD (mA) 2.44 2.46 2.48 2.5 2.52 2.54 2.56 2.58 2.6 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) VDD=4.75V VDD=13.2V IINQL (mA) 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) VDD=4.75V VDD=13.2V IINQ (mA) 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) UVLO rise UVLO fall VDRVUVLO (V) 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) UVLO rise UVLO fall VDDUVLO (V) 12 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET Typical Characteristics Figure 9 LDO dropout and VDRV current limit Figure 10 VDRV regulation voltage Figure 11 VIHD, VILD Differential input logic for turn on and off VOH, VOL Logic “1” and logic “0” output voltage 4.75 4.755 4.76 4.765 4.77 4.775 4.78 4.785 4.79 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) VDD=4.9V, Ivdrv=20mA VDD=5.2V, Ivdrv=60mA VDD=5.5V, Ivdrv=100mA VDRV (V) 50 70 90 110 130 150 170 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) VLDO (mV) 140 160 180 200 220 240 260 280 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) VDD=13V VDD=5V ILDO (mA) 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 2 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) V_IHD V_ILD VIHD, VILD (V) 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35 37.5 40 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) V_OH V_OL VOH, VOL (V) 13 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET Typical Characteristics Figure 12 RSRC Output high internal resistance and RSNK output low internal resistance Figure 13 VCLAMP Miller clamp voltage threshold and RCLAMP Miller clamp internal resistance 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) RSRC (Ω) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) RSNK (Ω) 0.6 0.65 0.7 0.75 0.8 0.85 0.9 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) VCLAMP (V) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) RCLAMP (Ω) 14 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET General description 6 General description RIC70115 is a single channel gate driver suited for GaN HEMT and logic level Si MOSFET. It can work in low or high side applications. RIC70115 will be certified for use in space applications by Defense Logistics Agency (DLA) to MIL-PRF- 38535 Class V. 6.1 Radiation performance RIC70115 is designed to work in space and other applications where there are significant ionizing radiation and energetic particles in the environment that can affect microcircuit performance. RIC70115 will be characterized for operation up to a total ionizing dose (TID) of 100 krad(Si), with electrical parameters including limits post-irradiation. It will also be characterized for single event effects (SEE) up to 83 MeV·cm2/mg. The packaged versions of RIC70115 do not have any electrically floating metal, with all metal internally connected to a known, controlled potential (such as the metal lid). This allows for compliance with system level requirements prohibiting electrically floating metal without the need to add additional wires. 6.1.1 Total ionizing dose (TID) RIC70115 was tested over total ionizing dose (TID) to verify robustness to ionizing protons and electrons within radiation environments, such as space. The radiation hardness assurance (RHA) program at IR HiRel uses a Cobalt-60 (60 Co) source and heavy ion irradiation. Every wafer is tested per MIL-STD-883, Method 1019, test condition A “Ionizing Radiation (Total Dose) Test Procedure.” Both pre- and post-irradiation performance were tested to the limits specified in the electrical characteristics. 6.1.2 Single event effects (SEE) RIC70115 was characterized in heavy ion environment for single event effects (SEE) up to a linear energy transfer (LET) of 83 MeV·cm2/mg. RIC70115 is immune to destructive events single event burnout (SEB), single event gate rupture (SEGR) and single event latch-up (SEL) over the full operating range of RIC70115 up to an LET of 83 MeV·cm2/mg. RIC70115 was also characterized for single event transient (SET) up to an LET of 83 MeV·cm2/mg. 6.2 Input power and bias 6.2.1 Internal LDO RIC70115 features an internal LDO that steps down an external voltage from VDD to a tightly regulated 4.8 V drive voltage on VDRV. This 4.8 V drive voltage on VDRV is used for gate drive on SRC. Additionally, this internal LDO can power other loads by applying load to VDRV. The internal LDO has a current limit ILDO, after which the LDO will enter constant current mode. When the internal LDO is used to generate VDRV voltage, a ceramic capacitor or similarly low ESR capacitor of at least 2 μF is recommended on VDRV for proper operation. 6.2.2 External bias RIC70115 can alternately work with other drive voltages, such as 5 V, by externally applying the input voltage on both VDD and VDRV. This will bypass the internal LDO, allowing the drive voltage to be the externally applied voltage. 15 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET General descriptionVDD RIC70115 IN+ IN- VSS VDRV SRC SNK CLAMP COM VIN VBIAS Figure 14 Example external bias where drive voltage is VBIAS 6.2.3 Negative drive RIC70115 can optionally provide a negative drive voltage if an external negative voltage is applied to the COM pin. This allows for improved robustness against induced turn on but at the expense of increased third quadrant “body diode” forward voltage drop loss.VDD RIC70115 IN+ IN- VSS VDRV SRC SNK CLAMP COM VIN VBIAS VNEG Figure 15 Example configuration with negative turn off VNEG 6.3 Input RIC70115 features TDI, where the input logic is a differential voltage from IN+ to IN- pins. TDI improves robustness against common mode noise up to 150 V static and 200 V dynamic, enabling both low and high side operation without the need for external level shifting, like a digital isolator. For proper operation an external resistor is required for any input that a voltage is applied on. 6.3.1 Minimum input pulse To help prevent spurious switching during common-mode transient events, RIC70115 features programmable input blanking time. When enabled, the blanking time will prevent any input pulse that is shorter than the blanking time from propagating to the output. Blanking time is set by connecting CONFIG 3, CONFIG 2 and CONFIG 1 pins to either VSS or open. All CONFIG pins have an internal pull up resistor. 16 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET General description Table 8 Blanking time based on CONFIG pin settings CONFIG 3 CONFIG 2 CONFIG 1 Blanking time Open Open Open 0 ns Open Open VSS 20 ns Open VSS Open 37 ns Open VSS VSS 58 ns VSS Open Open 77 ns VSS Open VSS 97 ns VSS VSS Open 116 ns VSS VSS VSS 135 ns 6.3.2 Selection of TDI input resistors RIC70115 requires precise input resistors on the IN+ and IN- pins. Even if the application does not require TDI (e.g. low side operation), the input resistors are still required. The input logic thresholds at the IN+ and IN- pins are designed to be paired with the specified input resistor values. These input resistors should be selected with a 0.1% tolerance, especially in high-side applications, where the common-mode voltage rating is contingent upon tight matching of input resistors. Extra care should be taken to ensure that these resistors are symmetrical, so that stray capacitance across them is also tightly matched. Table 9 shows the recommended values of TDI resistor for two different logic voltages. Table 9 Recommended TDI resistors Logic voltage (V) Rin+=Rin- 3.3 47 kΩ 5.0 75 kΩ In high-side applications, the input resistors must also be rated for the power dissipation expected in the worst-case operating conditions. The common-mode voltage observed by the high side transistor is “blocked” by each input resistor, so that RIC70115 is not exposed to the high voltage. The resistors dissipate power during the intervals where common-mode voltage is high, typically during the high-side transistors’ duty ratio of each switching period. The power rating of the resistors should therefore be selected based on the following equation. 𝑃𝑅𝑖𝑛+ = 𝑃𝑅𝑖𝑛− = 𝑉𝐷𝐶,𝑚𝑎𝑥2 𝑅𝑖𝑛+ ⋅ 𝐷 Where, • PRin+ is the required power rating for the input resistor on the IN+ pin in watts (W) • PRin- is the required power rating for the input resistor on the IN- pin in watts (W) • D is the high side duty ratio • VDC,max is the maximum expected DC bus voltage, experienced as common mode voltage during the high-side duty ration in volts (V) It is important to consider that the duty ratio may not be constant, so D should be selected as the duty ratio when operating at the maximum DC bus voltage. The following table lists some examples for selecting the input resistors, 17 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET General description based on logic voltage level, expected DC bus voltage and duty ratio. For most applications, the power requirement is quite low, thereby allowing the designer to select very small resistor packages such as 0402 or 0603. In some extreme scenarios with a high DC voltage and high duty ratio simultaneously, larger packages with higher power ratings may be needed. Table 10 Examples for selected input resistors Maximum DC bus voltage Logic voltage Duty ratio TDI input resistance Resistor tolerance Minimum Rin power rating 60 V 3.3 V 0.25 47 kΩ 0.1% 0.02 W 60 V 5 V 0.25 75 kΩ 0.1% 0.01 W 80 V 3.3 V 0.25 47 kΩ 0.1% 0.10 W 80 V 5 V 0.25 75 kΩ 0.1% 0.06 W 6.3.3 Low side In low side operation, differential input logic from IN+ to IN- is used to improve immunity to any common mode noise, such as ground bounce.VDD RIC70115 IN+ IN- VSS VDRV SRC SNK CLAMP COM VIN VBIAS Figure 16 Example configuration for low side drive with differential input 6.3.4 High side The common mode voltage (VCMR) support of up to 150 V static and 200 V dynamic allows RIC70115 to work in high side applications without the need for any logic level shifting device, such as a digital isolator. The high voltage is “blocked” by external resistors on IN+ and IN-. To prevent any noise from being applied to the input pins due to imbalance on the input (such as tolerance variation between input resistors) or noise during the switching transition, blanking time can be set on RIC70115. The amount of blanking time is adjustable, with fixed values from 0 ns to 135 ns programmable by connecting various CONFIG pins to VSS or leave open, details of which are in Table 8 18 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET General descriptionVDD RIC70115 IN+ IN- VSS VDRV SRC SNK CLAMP COM VDD RIC70115 IN+ IN- VSS VDRV SRC SNK CLAMP COM VIN VIN High voltage offset VDD SW +VCMR- Figure 17 Example configuration for high side drive 6.3.5 Optional additional input filter To improve performance by reducing single event transient (SET) events, an additional resistor and capacitor filter can be optionally added on the input IN+ and IN- pins as shown in Figure 18. The input resistors RIN+ and RIN- can be reduced with the following equations for 3.3 V and 5 V input logic. Reducing the input resistors RIN+ and RIN- improve SET performance but cause higher power loss during high side operation and require more drive current from the input logic source (VIN). The optional filter capacitance is recommended to be 40 pF and can be adjusted. 𝑅𝐹𝐿𝑇 3.3𝑉 𝑙𝑜𝑔𝑖𝑐 = 𝑅𝐼𝑁 47𝑘Ω − 𝑅𝐼𝑁 ⋅ 1.5𝑘Ω 𝑅𝐹𝐿𝑇 5𝑉 𝑙𝑜𝑔𝑖𝑐 = 𝑅𝐼𝑁 75𝑘Ω − 𝑅𝐼𝑁 ⋅ 1.5𝑘Ω Where, • RFLT is the resistance of the optional input filter in ohm (Ω) • RIN is the resistance of the input resistor RIN+ and RIN- in ohm (Ω) and cannot exceed 47 kΩ for 3.3V logic and 75 kΩ for 5V logic 19 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET General descriptionVDD RIC70115 IN+ IN- VSS VDRV SRC SNK CLAMP COM VIN VBIAS SW VBUSOptional input filter Optional input filter SW SW Figure 18 Example configuration for high-side drive with differential input Note that adding this optional input filter will extend matching delay, requiring additional dead time in the low tens of nanoseconds. Additionally, if the device is operating in low-side or a lower high side voltage (like a 28 V bus with DC max of 40 V), the external input resistor RIN+ and RIN- resistance can be reduced. 6.4 Output RIC70115 features a 1.5 A peak source and 2.5 A peak sink gate drive strength. The source and sink drive are independent pins, allowing the user to set the desired turn on and off slew rate with external resistors. 6.4.1 Miller clamp In some applications, such as GaN HEMT where there is a high voltage slew rate on the drain when the GaN HEMT is being held off, an induced voltage can be generated on the gate of the power switch. If not properly accounted for in design, this induced voltage can be high enough to cause the GaN HEMT to cause cross-conduction. To prevent this, RIC70115 includes an integrated Miller clamp on the CLAMP pin. The Miller clamp is on a separate pin that activates after the switch is fully turned off. This allows the turn off speed, which is determined by SNK and any external resistance on it, to be set at the desired speed for the turn off switching transition. Once off, the miller clamp enables, greatly reducing the impedance between gate to source, preventing induced voltages from rising high enough to causing cross-conduction. 6.5 Fault protection RIC70115 features two integrated fault protections, VDD undervoltage lockout (UVLO), VDRV undervoltage lockout (UVLO) and overtemperature protection (OTP). VDRV UVLO prevents RIC70115 from operating unless the VDRV voltage is sufficiently high enough, which protects against an insufficient gate drive voltage from not fully turning on the switch. If the switch is not fully turned on, the RDS(on) and power loss in the switch will be much larger than expected. OTP protects RIC70115 from operating at junction temperatures that exceed 150°C, which is outside of the absolute maximum ratings of the device. 20 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET Package details 7 Package details 7.1 LCC Figure 19 16 pin LCC package outline 21 2026-09-18 RIC70115 Rad hard high/low side gate driver for GaN HEMT and LL Si FET Package details Revision history Document revision Date Description of changes 06/18/2026 Datasheet (PD-98045) Rev A 09/18/2026 Updated based on ECN-Z8F80984742 Important notice Warnings Edition 2026-09-18 Published by International Rectifier HiRel Products, Inc. An Infineon Technologies company El Segundo, California 90245 USA © 2026 Infineon Technologies AG. All Rights Reserved. Do you have a question about this document? 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