Control of subthreshold leakage in standby mode is best accomplished with power-shutoff switches. But what can be done when the chip is fully awake and active?
One approach is gate-length biasing, which is a way to achieve leakage reduction in a way that will minimally disrupt performance. The effects of gate-length biasing, long known to analog designers, are multifold. While lengthening a given gate can exponentially reduce leakage as well as process variability, it also linearly reduces drive strength.
So in the view of Blaze DFM, whose Blaze MO tool performs gate-length biasing during application of optical-proximity correction, the answer lies in applying the technique as judiciously as possible. "In looking at the design, we know which are the critical paths and which are not," says Dave Reed, vice president of marketing and business development (and a founder) of Blaze DFM.
"Applying gate biasing to devices in timing-critical paths impacts the overall design performance, so we don't modify these," Reed says. "We want those at full speed. The ones that are in non-critical paths can be slowed without impacting performance."
Blaze MO can also perform voltage-threshold reassignment, using a similar approach to the one for gate-length biasing. "For non-critical paths, we can switch from low-VT to high-VT cells," says Reed. Low-VT cells are very fast but also very leaky, while high-VT cells are slower but leak less.
