Conversion Compliance For Power Over Ethernet

Victor Guijarro looks at the design and experimental results of an isolated dc-dc converter that can be used in powered devices in Power over Ethernet applications.

See Figure 1

IEEE Standard 802.3af defines the specifications and protocols for distribution of low power (

For example, applications such as Voice over Internet Protocol (VoIP) and LAN wireless are expected to grow to 18 million units by 2007. Furthermore, PoE would eliminate the need for many ac adapters as well as ac ports in remote locations.

Power Source Equipment (PSE) is the device that provides the power source, and Powered Device (PD) is the network peripheral device at the other end of the cable that is able to accept the power.

These PDs can be web cams, VoIP telephones, Wireless LAN access points and other appliances.

The flyback topology has traditionally been the designer's choice for low-power (below 50W) isolated converters. It requires only one magnetic component and one output rectifier, so it has the advantages of simplicity and low cost. Despite that, very high efficiencies can be achieved.

The basic specifications of the converter for a PD are an input voltage between 36V and 57V, 5V of output voltage, and 2.2A maximum output current.

High efficiency in a low-power converter is difficult to obtain due to the relatively high bias and control-circuit power losses with respect to the output power, which has a bigger impact during operation at low loads. In this case, the problem is worse due to the added bias power lost in the interface circuit for PoE compliancy. Careful specification/selection of the transformer and the switching MOSFET reduces low-power losses. In addition, switching-frequency reduction techniques at low load can be used to save power.

When a PD is plugged into a PoE system, there are three distinctive phases that occur in sequence. They are detection, classification, and power turn-on, which also should comply with certain timing.

Detection: The detection criterion by which a PSE accepts a PD is as a valid signature resistance. The signature resistance used is 24K9, which is within the PD detection range. In order to save power losses, we disconnect this resistor when input voltage is above 30V, saving about 85mW of power.

Classification: Class 0, or maximum power class by default, there is no need to provide any additional information to the PSE, so circuit is simplified.

Power turn-on circuit: The PSE supplies a minimum of 44V, however in order to account for the losses in the Ethernet cabling, connectors, transmission lines, transformers, and rectifiers, the PD power supply should work from a minimum of 36V. This circuit isolates the PD from the PSE during the detection/classification stages. Effectively, this is an undervoltage lockout that turns on the MOSFET Q1 when the input voltage is above 30V.

After power is finally released from the PSE, the regulator formed by R21 and Q5 provides the initial input voltage for the control circuit. The current charges the PWM IC decoupling capacitors until its UVLO level is reached and the PWM starts switching.

Once it starts switching, the voltage developed via the auxiliary winding reduces the VGS voltage of MOSFET Q5 until it turns off. This stops current from flowing through the bleeding resistor and, consequently, saves some power losses. The IC PWM controller will activate the converter as soon as the voltage on pin VCC reaches the VCC (start) level of 11V. To prevent transformer rattle during hiccup, the transformer peak current is slowly increased by the soft-start function.

The transformer in a flyback converter is probably the most critical part of the design. The first decision to make concerns the maximum operating duty cycle allowed (in this case less than 50%). This will give us the transformer ratio required. Secondly, the transformer magnetising inductance is selected in order to achieve continuous conduction at medium and high load. As a consequence of those design parameters, a combination of currents in primary and secondary sides is obtained that provides the optimum operating point or "sweet spot" where the losses are the lowest.

Power-supply designers know how much the leakage inductance contributes to additional power losses, as does the increase of the voltage spike at the switching MOSFET's drain. Therefore, this leakage inductance should be minimised by interleaving with the primary winding divided in two halves.

The widely used EFD20 (Economic Flat Design) core shape provides significant advantages for miniaturisation of the power supply. (For more information, see "Magnetics Design" Philips Semiconductor Applications Note, 1995.) The final specification of the transformer includes an EFD20/AL250 ferrite core, and windings with Np=26, Np1=18, and Ns=8. To optimise the design, it is necessary to make a custom component. For this current design, Pulse has provided the custom parts.

The control section includes the Philips TEA1506 PWM controller IC and the feedback compensation circuit.

The GreenChip II is the second generation of green switched-mode power-supply (SMPS) control ICs. A high level of integration leads to a cost-effective power supply with a low number of external components. This PWM controller IC was selected based on its low cost and simplicity of use. The IC doesn't require the error amplifier inside, since it is used in an isolated converter.

The special built-in green functions allow the efficiency to be optimum at all power levels. When the IC is configured for operation in continuous conduction mode, the controller operates in fixed frequency mode (175kHz) at high and medium power levels. During low load conditions, as power level drops, the switching frequency is reduced.

Current-mode control is used for its good line regulation behavior. The internally inverted control voltage adjusts the on-time, which is compared with the primary current information. The primary current is sensed across external resistors.

For over-current protection (OCP), the cycle-by-cycle peak drain current limit circuit is activated after the leading-edge blanking time (which provides current-sense noise immunity). For over-temperature protection (OTP), the IC will enter the repetitive safe restart mode.

When trying to get the highest efficiency, the obvious solution is an n-channel MOSFET driven directly from the output pin of the PWM IC. This can be done without the use of an external driver. The selection of the MOSFET is based on a compromise between switching and conduction losses in order to minimise the total. The 200V MOSFET used in this case is the Philips PHK4NQ20T in SO8 package. This 200V MOSFET provides better than 80% voltage de-rating factor for increased reliability. Since there is a relatively small voltage spike and ringing at the turn off, a snubber is not needed. Thus, less dissipation exists and circuit design is simplified.

The reference design demo-board in Figure 2 was built with all surface-mounted components, except for the input/output pins and the test points. It was made in a standard FR4 PCB with two layers of 1oz copper. All power components are on the topside of the board; the bottom side contains most of the control circuitry.

Note from Figure 3 the very high efficiency obtained at low loads—in particular at no load—thanks to the frequency- reduction and pulse-skipping techniques. The results are better than the previous estimation; the discrepancy is mostly due to the pessimistic MOSFET losses prediction. The converter achieves similar efficiency at lower and higher input voltages.

Carefully selecting the components makes it possible to create a dc-dc converter for PoE Power Devices that offers the advantages of simplicity and low cost, in addition to being compact and highly efficient.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.