Dennis Monticelli, National Semiconductor’s chief technology officer, is happy to speculate about the coming year. Like other analog semi companies, National will continue to reduce power requirements, he said, adding that the company will introduce high-definition, broadcast video components that handle four times the bandwidth of standard-definition components at the same power. National also will offer new-generation cable equalizers that require no power at all.
“As the deployment of video-enabled portable devices continues to grow, we will see a dramatic increase in the infrastructure required to support them,” he said. “As a result, higher-efficiency switching regulators will emerge along with novel technologies for reducing power-supply size without compromising performance.”
Improving the Old
Analog Devices provided a different
perspective, homing in on the redesign of one group of
products to illustrate the idea that no design is ever really
finished. The objective was to make the company’s direct
digital synthesis (DDS) chips more attractive than phaselocked
loop (PLL) or FPGA alternatives in wireless and
portable devices.
ADI aims to do so by reducing power consumption while maintaining the DDS ICs’ intrinsic advantages. These include faster settling time and higher resolution than PLLs, as well as better spurious-free dynamic range and a smaller footprint than FPGAs with embedded DDS functions driving external DACs.
The power reduction was substantial. The first improved DDS, the AD9913, can operate with a 250-MHz clock while consuming as little as 50 mW. Yet ADI’s Jeff Keip says the power reduction is the sum of a number of incremental improvements. What’s intriguing about the new part is the effort that went into cleverly resolving a situation that few would have considered an issue.
Architecturally, the AD9913 resembles the earlier ADI DDS chips, down to its 32-bit tuning word (Fig. 1). What’s different is the way it lets users precisely hit certain frequencies. Sometimes, 25.000000023283064365386962890625 MHz isn’t precise enough when you start with a 250-MHz clock and want to generate a sinewave of precisely 25 MHz.
To understand what the engineers did, look at that accumulator block at the top of the diagram. Apart from the tinted block, that’s exactly what’s used in all of ADI’s DDS ICs. On the surface, the synthesis process seems simple.
The output of the DDS, FO, is related to the clock frequency, FS, by FO = X/2C × FS. X is the frequency-tuning word, and C is the number of bits in the accumulator.
The accumulator recursively sums the digital input tuning word at the rate of the sample clock. This produces a time-series of digital words at the output of the accumulator that increases linearly until the accumulator rolls over at its maximum value of 2C.
Its output is truncated and fed into the angle-to-amplitude converter, which maps those words to one revolution on the unit circle. The output of the converter feeds an on-chip digital-to-analog converter (DAC). The average rollover rate of the accumulator determines the DAC output frequency.
In an ADI applications note, Ken Gentile provides a rigorous mathematical analysis that demonstrates that this approach cannot generate certain useful frequencies (FS/10, for example) because the accumulator modulus is fixed and the tuning word must be an integer.
The clever thing the ADI designers did in the new generation was to make the modulus adjustable. The app note also details how that makes it possible to synthesize the otherwise unavailable frequencies.
Making the accumulator modulus programmable requires a secondary accumulator (the tinted block in the figure). Figure 2 shows more details of the difference between the accumulators in previous DDS chips and the AD9913.
Fostering Collegiality
I first got interested in how
companies managed engineers
in remote design centers
(RDCs) when I talked to Kevin
Leary at Analog Devices in
2006 (see “Better, Faster, Cheaper”
at www.electronicdesign.com,
ED Online 14997). My interest
was reawakened last fall, when
Intersil invited me to a dinner
that was the capstone event to
a three-day internal consortium
for all of its designers from all
of its worldwide design centers.
For this issue, I sent out a questionnaire to multiple companies, asking how they created RDCs and how they managed the design process across all those borders.
First, I talked to Gerald “Woody” Smith at Analog Design Consortium (ADC) in San Jose, Calif., which is an ad-hoc organization of some of the best West Coast analog/mixed-signal chip designers. “A project may have RF blocks from Bulgaria, PLLs from Silicon Valley, and other analog blocks and digital blocks from Los Angeles, while using layout and fabrication resources in Taiwan,” Smith said.
Size affects attitudes about resources. “Today’s smaller design houses typically don’t have all the tools and specialties necessary in house,” Smith said. “Internally, ADC has a core competency that we feel gives us a market advantage. We outsource anything outside that competency or that is overly expensive.”
Smith was blunt about the cost of such outsourcing, admitting it typically adds an additional 20% overhead to project management.
Moving up in size, Silicon & Software Systems Ltd. (S3) in Ireland has been in the analog design services business since 1986. It now has an RDC in Silicon Valley. But recently, it was most excited about acquiring an RDC in Lisbon, Portugal—already a hotbed of analog chip design thanks to Chip Idea, which was recently acquired by MIPS.
According to senior project engineer Fionnuala Callan, S3 uses a set of Web portal services called S3 Engage. Designers can access this collection of project communication tools via a secure portal on the Internet. Functions include issue tracking, similar to ClearQuest and ProjectSynch, but with no limit on numbers of users. This addresses the need for “lunch-room” style communication.
“Many of the soft communication problems are overcome by the almost casual conversational approach adopted by users of this type of communications tool,” Callan said. “Issues are raised as they occur and all correspondence logged, so it’s transparent when things occur, and if they are delayed, where they are being delayed.”
The Big Leagues
Intersil has RDCs
in Dallas, Irvine, North Branch, and
Research Triangle Park in the U.S.
plus an offshore RDC in the U.K. and
two in India. The company’s main operations
happen at its offices in Palm
Bay, Fla., and Milpitas, Calif. According
to Neil Robinson, who manages the
company’s U.K. design center, Intersil
staffs its RDCs in different ways.
The core of the RDC in Hyderabad, India, is a group of designers shed from an independent design house. Other centers, like the RDC in Harlow in the U.K., were developed by focused recruiting. The U.K. operation was seeded by the targeted hiring of seasoned industry veterans from various IC design companies within the British Isles that formed a solid core of talent.
The company also works with universities, offering internships and postgraduate sponsorships to attract talented graduates. Intersil’s RDCs focus on products from one or two of the company’s product groups. Central technology groups provide a clearinghouse for technology issues like design-kit development, electrostaticdischarge (ESD) strategies, and cell libraries.
Typically, one RDC provides the bulk of design work for a given program. However, it is common for groups to share knowledge and resources. Some tasks, such as layout work or digital place and route, can be outsourced from one design site to another.
Linear Technology opened its first RDC in Singapore in 1991. Afterward, the company opened nine domestic centers, followed by its first European design center in Munich in 2006. According to Chris Mann, Linear’s director of satellite design centers, the company has never acquired a team from another company or an independent design house, nor has it ever used university-sponsored or breeder programs.
“Generally, the company identifies a few individuals either from headquarters in Milpitas or from outside the company and builds a team from scratch around them,” Mann said.
Organizationally, new design engineers are aligned to one of the company’s product groups and generally take their strategic direction from that group. Design managers within the product groups choose projects, which the central product group and the local team manage collaboratively.
“Each week, each product group initiates a conference call with each RDC and reviews each product that is currently in development,” Mann said. “Live formal design reviews are held for each project either in Milpitas or, more often, locally at the larger design centers.”