Several methods exist for selecting the MOSFETs required in dc-dc synchronous buck converters. These techniques generally target selection for highest efficiency or focus on determining the losses involved in the power conversion process. However, many methods include antiquated loss mechanisms, particularly for the control FET (or high-side MOSFET). Also, the switching losses of the sync FET (or low-side MOSFET) have been assumed to be near zero since the addition of anti-parallel diodes across the drain and source connections.
This article updates the traditional thought process about where high-side losses are occurring, the impact of stray inductance, and limitations on slew rate. Additionally, it introduces a new method for selecting components very quickly and easily. The new set of formulas for estimating switching losses, which also accounts for the interplay between silicon technology, packaging, layout, and application conditions, is provided as well.
Predicting buck converter efficiency and understanding the contributions to overall system power loss, which originate from passive components and the power MOSFETs, are important for every design. With the dramatically reduced switching times available in state-of-the-art power MOSFETs (25/30 V), we see dramatic differences when calculating turn-on and turn-off losses of control FETs in buck converters.
MOSFET power losses are separated into three categories: switching, conduction, and driVIng losses. Depending on load conditions, one of the three contributors dominates. Designers can assume that the turn-on cycle dominates high-side losses, but experiments and simulations indicate that the interaction between the system layout and power MOSFET must be considered. The turn-off cycle now clearly dominates the losses that impact efficiency estimations and thermal design.
Figure 1a shows what is known as the classic picture of switching power MOSFETs. When the MOSFET turns on, the potential between gate and source (Vgs) reaches the threshold voltage (Vth) and the current starts to increase. When Vgs increases to the Miller plateau (VMiller), the current has reached its final value and the voltage across the MOSFET (Vd,s) starts to drop until the end of the Miller plateau. This simultaneous occurrence of voltage and current (VI) creates the switching losses during turn-on, as indicated by the shaded region in Figure 1a.
In the classic model, turn-on switching losses exclusively depend on MOSFET parameters, VIn, IOut, switching frequency, and time. This model does not account for package choice or printed-circuit board (PCB) layout, which always impacts performance. Figure 1b illustrates the impact of parasitic stray inductance (LStray) in the commutation loop of the buck converter on these switching waveforms. Now when the MOSFET turns on, the current slew rate is considerably lower than expected, since stray inductance limits the rise time. Energy dissipated during turn-on for inductive limited circuits becomes insignificant.
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The same considerations regarding current slew rates apply during the turn-off cycle. The MOSFET will allow a faster current decrease than the stray inductance allows, which results in the switching waveforms depicted in Figure 2b. These waveforms show that during the turn-off period, the slew rate is limited by stray inductance. This enlarges the overlap of current through the MOSFET at the time when we have maximum voltage across the device. Our new calculations for losses must account for the package parasitic inductance and any PCB layout-related losses.
Utilizing A Power Budget
MOSFET selection begins by defining some power-supply parameters, including target efficiency: VIn, VOut, and IOut. Target efficiency is assumed to be at full load, similar to the typical curve seen in Figure 1. Efficiency at any point can later be calculated as well. We immediately calculate the output power required by the supply:
Additional input power is required, since we will never reach 100% efficiency. The designer will need to select an appropriate starting point for efficiency (we use 85% for this example) and divide the output power by the efficiency to determine the input power required:
The total power loss of the supply is the difference between input power and output power. Power loss is due to the input capacitance, pulse-width modulation (PWM) controller, driver, MOSFETs, PCB, output inductance, and output capacitance:
This calculated “total power loss” is effectively our power budget. This is the wattage that we can “spend” designing the power supply. Losses due to the MOSFETs are in the 40% to 60% range of the total power lost. If we can select MOSFETs that use 40% of the total loss, this will leave 60% for all other losses in the system:
We need to split this amount across all MOSFETs. Optimum design would dictate splitting this power evenly across the MOSFETs to allow for equal thermal dissipation. Initially, it is best to start with 50% of the power split between the high-side and low-side MOSFETs. Ultimately, the procedure is iterative, so you can change these proportions later. We now have “power budgets” for both the high-side and low-side devices as given:
With the power “budgets” determined, we now need to analyze the loss mechanisms separately for the high-side and low-side device.
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High-Side MOSFET Loss Mechanisms
The power utilized by the high-side MOSFET is approximately equal to the sum of the four dominant sources of power loss in high-side devices:
Each loss parameter contributes in varying proportions to the total loss of the high-side MOSFET. To begin the selection process, arbitrary percentages need to be assigned. These values will change significantly by vendor, package type, technology, and other factors. Proportions should be initially assigned as (60%, 25%, 10%, 5%). The governing equations can be algebraically manipulated and solved for parameters found on a typical datasheet:
Low-Side MOSFET Loss Mechanisms
Similarly, there are several sources of power loss in the low-side devices. These sources are related to switching, static, and reverse-recovery losses of the antiparallel diode, switching, and conduction losses. Switching losses are very minimal, primarily because of the anti-parallel diode implemented in N-channel power MOSFETs, and they can be considered as zero. To that end, the total low-side losses are approximated by diode plus conduction losses:
The middle equation of Equation 16 can be algebraically rearranged and solved for RDS(ON) so that we can select our low-side MOSFET:
The datasheet rarely provides detailed specifications of the antiparallel diode. Therefore, we must approximate the breakdown voltage (VBreakdown). 700 mV is a fair approximation for VBreakdown. Controller deadtime (tDeadtime) will vary based on the controller, but for simplified calculations should be in the 40- to 60-ns range. Using 700 mV and 40 ns as our approximations, the third equation of Equation 16 will reduce as follows:
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Notice that Equation 17 does not include parameters for the MOSFET. Output current could arguably include the ripple current. However, this complicates our calculation and won’t greatly impact the accuracy of our results.
We will calculate junction temperature during the final step. However, it is important to realize that the RDS(ON) arrived at in Equation 17 should be modified to reflect device operating temperature well above 25°C. We either need to implement a temperature compensation coefficient (TCC) or understand what value to look for on the datasheet.
Although RDS(ON) is not linearly rising with temperature, we will have two basic data points. Nominally, the value given on the datasheet is at 25°C, while our calculations are near TJmax. It will be easiest to use a TCC (1.3 for our example) so our task of finding a device is greatly simplified.
TCCs are usually the same for a family of devices from a given vendor. Determining the TCC is quite simple:
Once you get familiar with the entire process, you can adjust TCC (since TJmax may be different than 105°C) or more accurately calculate the values directly. The goal is to get to 90% of the decisions in 10% of the time. We can now look for devices where the low-side power loss is less than or equal to our low-side power budget.
Working Through An Example
The process is iterative. We define our condition, create our loss budget, and initially select components. We then calculate the losses from datasheet specifications and begin to make tradeoffs between package, layout, high-side versus low-side choices, and other factors. In this example, we target a 20-A supply with the following requirements:
VIn = 12.0 V dc
VOut = 1.2 V dc
IOut = 20.0 A dc
Switching frequency = 300 kHz
Vgs = 5 V dc
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Ta = 55°C
TJmax = 105°C
Output inductance = 300 nH
Efficiency target = 85%
We first calculate our power budgets for the high-side and low-side MOSFETs. Then we need to assign percentages to the top four high-side parameters, using 60%, 25%, 10%, 5% as starting values (Equation 19).
Multiplying by frequency, rather than dividing by the period, simplifies the calculations. Current through the output inductor is approximately the output current plus half of the ripple current. The latter term is calculated by Equation 20.
The RDS(ON) values determined above are at elevated temperatures, while the manufacturer’s datasheet values are specified at 25°C. We will need to use a TCC to find these approximate values on a datasheet (Equation 21).
We now have enough information to start our search for devices. We can begin with either the high-side or low-side device. For this example we begin the iterative process by selecting a super-small-outline (SuperSO8) device in Infineon’s OptiMOS3 30V family for the low-side MOSFET.
Our design specifications indicate 5-V gate drive, while the datasheet specification for RDS(ON) is given with 10-V gate drive (Vgs). This is normal across most suppliers. Knowing this, we selected the BSC016N03MSG, which will have an RDS(ON) at 25°C with Vgs = 5 V of 2.0 mΩ.
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Selecting the high-side MOSFET is nearly as straightforward. RDS(ON) is a common starting point. However, since we now recognize the significant losses caused by layout and package, we need to evaluate our package options first. We have previously determined that to stay within “budget” (for the given proportions), we need a combined inductance value less than 4.7 nH. The table provides nominal values for package inductance. (Drain and source inductance can be summed to simplify the calculation.)
From the table it is evident that the D-PAK would require a nearly perfect PCB. Layout for these devices is more complicated since the drain, gate, and source pins are all located on the same side of the device. This increases parasitic inductance more than all other options. SuperSO8, S3O8, or CanPAK are all manageable options for this design, leaVIng about 4 nH for PCB stray inductance. For this example, we have decided to use the 3- by 3-mm package (S3O8) on the high side. This package provides lower parasitic inductance than the SuperSO8 and utilizes less board space. The extra copper area will help with heat dissipation.
Proceeding with the RDS(ON) parameter (again taking note of the 25°C value at Vgs = 5 V), we start our search for high-side devices. From Infineon’s Web site (www.infineon.com), we select the BSZ035N03MSG, which will have RDS(ON) at 25°C with Vgs = 5 V of 4.3 mΩ, LPackage = 0.2 nH, LPCB = 4 nH, Qg = 56 nC, and QOSS = 32 nC. We need to use the original power-loss equations to calculate the losses (Equation 23).
The calculated sum of the losses of both devices equals 2.025 W. This exceeds our original budget of 1.68 W. We determine that these MOSFETs will use about 43% of the overall budget, not 40% as we had targeted. There are endless permutations where we can decide to utilize higher percentage splits and better devices, allow more of the overall budget for MOSFETs, and so on. We would have a full 2.5 W to utilize for the MOSFETs if we adjust our initial conditions to 60% for these devices.
Finally, we will need to estimate the temperature of the devices to ensure that we have made good choices. Designers can estimate the junction temperature by multiplying the dissipations value by the junction-to-ambient value given in the datasheet and then adding the ambient temperature (Equation 24).
The calculations yield reasonable values for junction temperatures. Spice simulations yield values within 5% of these solutions, while taking significantly longer. Of course, we need to correlate against calculations and then build, test, and verify our choices. The above method has provided a straightforward process for selecting MOSFETs in a dc-dc synchronous buck converter.
For more, see “Selecting Protection Devices: TVS Diodes vs. Metal-Oxide Varistors” by Steven J. Goldman at powerelectronics.com/power_management/regulator_ics/selecting-protection-devices-201006/index.html.