To illustrate the factors that play a role in a buck converter’s efficiency, the Table below lists the equations used to estimate the most significant power losses. The parameters to minimize for high efficiency can be quickly determined utilizing these equations. The dominant losses in a buck converter design depend on the specific operating conditions of the circuit, and hence, it is important to perform the calculations below for your application. You can click on the table to enlarge it for easy viewing.
From these equations, the following parameters can be used to improve the efficiency of a buck converter. Keep in mind that typically the output voltage and current are fixed by the load requirement.
Parameters to Minimize for High Efficiency
Switching Frequency (fSW)
Decreasing the switching frequency will decrease the losses in the MOSFETs, rectifier and the inductor core. Practical considerations usually limit the switching frequency. As the switching frequency decreases, the inductance and capacitance must increase in order to
maintain an acceptable amount of inductor current ripple and output voltage ripple. As a result, the physical size of the inductors and capacitors will increase, and may not be acceptable in some applications.
At low switching frequencies, the conduction losses will dominate and little is gained by decreasing the switching frequency any further. In the majority of point-of-load applications, an acceptable lower frequency range is approximately 150 to 350 kHz.
Switching frequencies much greater than 350 kHz are possible while maintaining good efficiency as long as care is taken in selecting MOSFETs. Today’s MOSFETs allow for reasonable efficiencies at switching frequencies reaching 1.5 MHz without a substantial cost penalty.
Both conduction and switching losses can be significant in the high-side MOSFET. Conduction losses are proportional to the RDS(ON), whereas switching losses are proportional to the gate charge, QG, of the MOSFET. Unfortunately, for a given MOSFET fabrication process, low RDS(ON) devices will tend to have a higher gate charge and vice versa. Deciding which MOSFET parameter is best to optimize depends on the duty cycle and switching frequency. For low duty cycles (< 0.5), switching losses tend to dominate, especially at high frequencies. In this case, it is important to minimize the gate charge. For high duty cycles, conduction losses play a larger role, and it is important to minimize the RDS(ON).
Unlike the high-side MOSFET, the voltage across the drain-to-source of the low-side MOSFET is much lower during turn-on and turn-off transitions due to the conduction of its body diode during the dead time. As a result, switching losses in the low side are often negligible. This is fortunate since the calculations for the low-side switching losses are much more complex (see Reference 2). It is most beneficial to select a low-side MOSFET that has the lowest achievable RDS(ON). Low RDS(ON) MOSFETs require larger die area, and as result, can be expected to be in a larger IC package and be relatively more expensive.
To ensure the contribution of the body diode is minimal, a low forward voltage Schottky diode should be placed externally across QLS or select an integrated MOSFET + Schottky device.
The power lost in the diode is largely determined by the forward voltage, VF. A Schottky diode should be used whenever possible since it has a very low forward voltage (~ 0.3V) and minimal reverse recovery time.
Synchronous versus Non-Synchronous
In most applications, especially those that operate at low duty cycles and near the full load current, a synchronous buck will be more efficient than a non-synchronous buck. Non-synchronous bucks can sometimes deliver a higher efficiency when operating at lighter loads or at very high duty cycles. For more details see Reference 3.
Inductor power losses are mainly a result of the DC resistance of the winding, DCR, and hysteresis within the core magnetic material. To decrease the DC conduction losses for a given inductance, a larger diameter wire for the coil should be used. To minimize the core losses a lower switching frequency should be selected. Both of these will result in a physically larger inductor that may be more costly but will achieve better efficiency. For more details on inductor power losses see Reference 1.
To identify an inductor with a low DCR rating, look for one with a current specification that is higher than is required for the buck design.
The methods described thus far can provide large efficiency gains if appropriate design practices are utilized. There are many additional losses throughout a real switching buck converter circuit that can also be reduced with some detailed analysis. Reducing these may only provide little return; however, they should be considered if the operating conditions are atypical or to achieve maximum efficiency.
Additional Power Losses in a Buck Converter
● PCB trace copper losses ●Charging HS MOSFET’s output capacitor
●Controller quiescent current ●Charging external Schottky diode’s capacitance
●Gate drive losses ●Reverse recovery losses of body diode
●Input and output capacitor ESR losses
1. Eichhorn, Travis. “Estimate Inductor Losses Easily in Power Supply Designs”, Power Electronics Technology, April 2005.
2. Klien, Jon. “AN-6005 Synchronous Buck MOSFET Loss Calculations with Excel Model”, Fairchild Semiconductor, January 2006.
3. Nowakowski, Rich and Tang, Ning. “Efficiency of Synchronous versus Nonsynchronous Buck Converters”, TI Analog Applications Journal, 4Q 2009.
4. Application Note 4266, “An Efficiency Primer for Switch-Mode, DC-DC Converter Power Supplies”, Maxim Integrated Products, Dec. 2008.
Chris Cooper is the technology director for power at Avnet Electronics Marketing Americas. Chris provides design support and specializes in power technology. He has a Bachelor’s degree in Electrical Engineering from Memorial University of Newfoundland.