Electronic Design

High-Voltage And Power Elements Are Combined In Fine-Line CMOS

At the recent International Symposium on Power Semiconductor Devices (ISPSD) in Toulouse, France, STMicroelectronics disclosed the results of implementing high-voltage LDMOS power transistors in a 0.35-µm CMOS process. This implementation is part of the company's new generation of multipower bipolar-CMOS-DMOS (BCD6) technology. By using deep-submicron lithography, researchers incorporated 60-V LDMOS structures on a silicon substrate that includes low-voltage CMOS circuits.

To realize these devices, STMicroelectronics took the triple-well route. Unlike the previous-generation smart-power process, BCD5, the BCD6 scheme builds twin retrograde wells and a buried n well on a p over a p+ substrate without any specific epitaxial-layer growth and junction-isolation steps. While the high-voltage n-channel LDMOS uses a dedicated n well as a drain region, the p-channel version uses a p well as a drain.

Also, the BCD6 utilizes a large-angle tilt-boron implantation that's self-aligned to the gate, masked by photoresist material, to achieve both n-channel and p-channel power LDMOS body regions. Alessandro Moscatelli, VLSI BCD process development engineer at STMicroelectronics, says that the company used an angle larger than 7° with respect to the vertical.

Researchers obtained a low threshold voltage for the LDMOS device by subjecting it to different tilt angles with different doses and implant energies. This eliminated the source-to-drain punch-through effect. It also minimized drain-induced barrier lowering (DIBL) and IOFF current.

The LDMOS employs adaptive reduced surface-field techniques to maximize on-state breakdown voltage, which sustains a high voltage with a very thin gate oxide (7 nm). In reality, the drift drain region and the thick field oxide sustain any high voltage that's applied to the drain terminal of the LDMOS. Using these techniques, researchers successfully implemented a 40-V n-channel LDMOS device in BCD6 technology. Furthermore, enlarging the drain drift region by about 20% with the same well doses can extend the device breakdown voltage to over 60 V.

The BCD6 technology also employs a clever metallization scheme to cut the metal interconnect resistance contribution to the device's on-resistance by about 25%. Five aluminum/copper metal levels are used in the power section with an interdigitated layout. The first, second, third, and fourth metal levels contacting drain and source fingers are stacked. Meanwhile, the 3-µm-thick fifth metal layer carries the current to the pads. A 60% improvement in metal contribution to the on-resistance was observed by simply replacing the 3-µm thickness of the fifth metal level with a 5-µm-thick copper metal interconnect (see the figure).

Finally, the new smart power process employs a self-aligned silicide technique in building the LDMOS structure. This enhances the device's robustness and operating speed. Due to very low silicide sheet resistance, a uniform potential distribution is achieved, improving the device's ruggedness during high-current operations.

STMicroelectronics isn't alone in realizing this level of smart power integration, though. Motorola unveiled its SMARTMOS7 process technology at ISPSD as well. This development can handle 65-V LDMOS devices (see "SMARTMOS Merges Analog And High-Voltage Power Components In Deep-Submicron CMOS," Electronic Design, July 24, p. 38).

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