Interconnect Manages Power And Data Flow

As systems-on-a-chip (SoCs) bring more functionality onto the chip itself, data flow becomes a daunting issue. To confront this design problem, Sonics, Inc. has come out with the SonicsMX solution. The goal of SonicsMX is to enable the design of low-power, cost-effective SoC devices to power multimedia-rich wireless and handheld products. By providing the needed physical structures, protocols, and power-management capabilities, the solution strives to overcome data-flow and other design challenges. Those issues are particularly associated with the convergence of multimedia and communications onto a single SoC.

SonicsMX was born out of a close collaboration with Texas Instruments. Specifically, TI wanted to ensure that Sonics' SMART interconnect solution would be suitable for the low-power operation required by advanced wireless and handheld applications, such as TI's OMAP platforms. The solution is based on Sonics' next-generation SMART interconnect technology.

SonicsMX is a low-power-consumption, flexible interconnect that supports cross-bar, shared-link, or hybrid topologies within a multithreaded and non-blocking architecture. It merges flexibility with advanced features like moderate clock rates, mixed latency requirements, and error management. The feature set of the SonicsMX boasts the following: threaded and non-blocking communications; full user control of latency, performance, and area; low power for maximum battery life; and QoS, access security, and error handling. As a result, SoC developers can tweak the interconnect for their own use. They also can manage all communications and multimedia-convergence data-flow challenges.

Through an active-decoupled approach, SonicsMX supports the OCP-IP 2.0 socket protocol. It therefore allows SoC developers to design cores and interconnect strategies in parallel. That active-decoupled approach is called Sonics Methodology and Architecture for Rapid Time to Market (SMART) Interconnects. It allows designers to utilize pre-designed, highly optimized and flexible interconnects to accurately configure, analyze, and verify data flows at the architecture phase (early in the SoC design process). In this phase of SoC development, the ability to configure and verify internal interconnects should dramatically increase the design's predictability.

In addition, the active-decoupled approach lets engineering teams fine-tune interconnect structures in parallel with core development and integration. Engineering productivity is thereby improved for a given SoC design and across a product line, as all of the elements are essentially reusable. Only incremental engineering effort is required. SonicsMX therefore works to accelerate product-family development. It provides simplified SoC core reuse together with flexible subsystem-based partitioning.

An integrated tool suite is available to configure SonicsMX for specific implementations. SonicsStudio is useful for analyzing data flows and executing performance-verification testing. To further facilitate system modeling and verification, a SystemC model is available for SonicsMX. It uses electronic-system-level products (ESL) from electronic-design-automation vendors. Called SonicsMXC, it can deliver outputs for ESL or register-transfer-level (RTL) environments. The same source can then be used for development, allowing software engineers and system architects to work in parallel.

SonicsMX is currently available. For further information and pricing, please contact the company.