Electronic Design

The Laptop Tug Of War: Speed Versus Battery Life

Stunning performance gains in the latest laptops create unprecedented power issues.

Last month, key players revealed their latest laptop developments at the Consumer Electronics Show in Las Vegas. Not to be outdone, Apple followed the show with some startling announcements of its own. What's the underlying trend developing from this flurry of activity? Simply, these laptops will boast performance far beyond their predecessors.

For starters, Intel used CES to debut its Centrino Core Duo mobile technology platform for thin and light notebook PCs. You may have heard of this platform under the "napa" codename. The dualcore, 65-nm, process-technology version of the Pentium M had been codenamed "yonah." Intel uses the "Core Duo" terminology to distinguish the technology from its single-core "Core Solo" version.

At the same show, Asus, Dell, Fujitsu, and Hewlett-Packard introduced their new laptop PCs based on the Intel chips. Dell's Inspiron E1705 will cost just under $2000, with the first units scheduled to ship on February 15. Without specifying ship dates, HP demonstrated its dv1000t (also designated the Compac v2000t), Fujitsu its LifeBook N6410 and LifeBook E8110, and Asus its W2J, A7J, W5F, and V6J laptops.

These CES announcements themselves were satisfying enough. But the following week, Apple blew the PC crowd away by showing two models of its new MacBook Pro, also with mid-February availability (Fig. 1). And for the first time ever, an Apple product was based on Intel chips—the Core Duo mobile technology platform. Steve Jobs boasted that the Intel chips provide a fourfold performance edge over previous-generation Apple laptops that used Power-PC processors.

So the Core Duo is the new star in the laptop galaxy, with dazzling capacity for graphics, multimedia, and other performance benchmarks. But all of that potential is pretty useless without corresponding developments in power management. That's necessary because when they're runing fullout, these chips use more power than their predecessors.

The dual-core processor's datasheet specifies a maximum 1.3-V VCC and a maximum ICC of 34 A for a theoretical maximum power consumption of 44.2 W. (Thermal design, though, is based on 31 W.) The maximum ICC di/dt slew is 0.6 A/ns.

By way of comparison, check out the highest-performance mobile processor previous to the Dual Core, the Pentium M. It specifies a 1.356-V maximum VCC and a 26-A maximum ICC for a theoretical maximum power of 35.3 W. Maximum di/dt is 0.5 A/ns, and the thermal design target is 27 W.

So compared to the Pentium M, the dual-core chip draws around 20% more maximum power and requires voltage regulation to respond about 16% more rapidly. From a thermal design standpoint, engineers are looking to shed about 13% more heat. Laptops live and die on battery life, which can be extended by power-saving techniques like those described below, but power-supply designers must account for those peak-demand numbers (see "Power-Supply Design Issues," p. 38).

Stretching Battery Life
Despite that peak demand, these laptops exhibit impressive battery life. The reductions in power consumption come from three components in the Centrino Core Duo platform: the Intel Core Duo processor itself, the Mobile 945 Express chip-set family, and the PRO/Wireless 3945ABG network connection.

The Core Duo processor is built on Intel's 65-nm process technology. It includes a power-optimized 667-MHz L2 "smart" cache, enhanced power management, and several power-saving features Intel calls "power coordination," "enhanced Intel deeper sleep with dynamic cache sizing," and "enhanced Intel SpeedStep technology."

Thanks to these features, the processor can operate at multiple voltage and frequency operating points with real-time dynamic switching of the voltage and frequency based on CPU demand. This occurs by switching the bus ratios, core operating voltage, and core processor speeds without resetting the notebook. It takes place under software control, with very low transition latency.

The 945 Express chip-set family hub architecture for notebooks, which includes a new graphics media accelerator, supports dual-channel DDR2 memory at 667 MHz. Additional support is included for native hardware acceleration of multistreaming media.

Power-saving features consist of Intel's "display power-saving technology 2.0" and a dual-frequency graphics technology. The former reduces display backlight power by up to 400 mW with minimal visual impact to the end user. The dual-frequency scheme enables the chip set to dynamically switch the render-clock frequency to match graphics workloads.

The third component of the Centrino-Duo mobile technology platform is the PRO/Wireless 3945ABG network connection (a PCIe mini-card). It supports features that let enterprise users exploit new IT administration tool capabilities and an application programming interface (API) built around 802.11e quality-of-service (QoS) for Voice over Internet Protocol (VoIP). It doesn't necessarily add any power-saving features.

Sleep Stages
The Core Duo processor can operate at very low voltages. Advanced techniques minimize clock and signal switching, which reduces power dissipation in the active state. The processor can quickly enter and exit from these states to save power while maintaining fast responsiveness. Low-power states comprise " stopgrant," "stop-grant snoop," "sleep," "deep sleep," "deeper sleep," and "deeper sleep low-voltage"(Fig. 2).

In the "stop-grant" state, snoops are serviced, and interrupts from the front-side bus (FSB) are latched. But only one of those interrupts will be serviced upon return to normal operation. The "stop-grant snoop" state is the response to a snoop. The core stays in this state until the snoop is serviced or an interrupt is latched.

In "sleep" state, internal clocks are shut down, and the core doesn't respond to snoops. But it does maintain context. "Deep sleep," a lower-power version of "sleep," eschews all transitions on the FSB. "Deeper sleep" reduces the core voltage. Two possible reduced levels exist. First, at the lower level, L2 cache is shut down and the state is called "deeper sleep low-voltage." Second, under some conditions, the processor can flush and disable a programmable number of L2 cache ways on each entry to the "deeper sleep" state.

Note that these explanations of the low-power states are very superficial, compared to the explanations in the datasheet. But they should provide a sense of the depth of low-power options available. For additional power savings, DDR2 memory self-refresh provides chip-set and dual-inline memory-module (DIMM) power savings by putting memory into a reduced power state when the display is still active on DDR2-based platforms.

Meanwhile, "dynamic bus parking" saves platform power by allowing the chip set to power down with the processor in its low-frequency powersaving states. Through "enhanced deeper sleep with dynamic cache sizing," the L2 smart cache can dynamically flush its ways to system memory based on demand or during periods of inactivity. Power savings occur as cache ways are turned off once the data is saved in memory.

L2 cache data integrity determines the "deeper sleep" minimum voltage limit for the processor. So once the dynamic cache sizing feature flushes the entire L2 cache to memory, the processor transitions to a new power-management state called "enhanced deeper sleep." In this state, the processor can lower its voltage below the deeper sleep minimum voltage.

Intel gave the Core Duo processor a new thermal-management system, the Advanced Thermal Manager. Each of the processor's cores features a digital temperature sensor and a thermal monitor. Located close to the hot spots on the chip, they enable more precise fan control. The processor also supports Intel's next-generation, dual-core optimized voltage regulator, Intel Mobile Voltage Positioning (Intel MVP VI).

A split-transaction, deferred reply protocol helps power-optimize the 667-MHz system bus. The system ( frontside) bus uses source-synchronous transfer (SST) for addresses and data. It transfers data four times per bus clock, and the address bus can deliver addresses twice per bus clock. Together, they provide a data-bus bandwidth of up to 5.33 Gbytes/s. Signal levels and timing consist of Advanced Gunning Transceiver Logic (AGTL+).

With all this, the new laptops will have as much battery life as their predecessors. But their power supplies still must support instantaneous demand.

TAGS: Mobile Intel
Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.