Electronic Design

Low-Power Design With Multi-V<sub>DD</sub> Flows

Nearly all designs at advanced process nodes need some sort of power-saving strategy. As more designs employ advanced low-power techniques, design teams are discovering huge implementation hurdles that affect cost, performance, and time to market. Current place-and-route solutions are severely limited due to aging architectures and inability of the core static timing analysis (STA) engines to represent more than a single mode/corner combination.

The basic low-power design techniques, such as clock gating for reducing dynamic power and multiple voltage thresholds (multi-VT) to decrease leakage current, are well-established and supported by existing tools for a single mode/corner combination. However, designers are running into difficulty with more advanced techniques such as designing for power in a multi-corner, multi-mode (MCMM) context, multi-voltage flows, and designing power-efficient clock trees. With a multi-voltage supply (multi-VDD) approach, some blocks use lower supply voltages than others, creating voltage "islands." This flow gets even more complex when dynamic voltage scaling is used to change the supply voltage level during operation. In this article, we discuss the multi-voltage flow in detail.

Multi-Voltage Design With MCMM
An increasingly common technique to reduce dynamic power is the use of multiple voltage islands (domains), which allows some blocks to use lower supply voltages than others, or to be completely shut off for certain modes of operation. This presents new challenges in physical design. Firstly, the tools need to correctly place and route across multiple domains and ensure that the timing and optimization engines honor the multi-voltage domain specifications. Secondly, the multi-voltage implementation system needs to ensure that the MCMM requirements are also satisfied in the same run. Basically, each additional voltage island causes the number of timing analysis mode/corner scenarios to double when all the minimum and maximum voltage combinations are considered (Fig. 1).

The core architectures of incumbent place-and-route solutions in the market are at least 10 to 15 years old and were intended to handle at most one or two scenarios. Physical implementation for ultra-low-power (ULP) designs must be capable of concurrently analyzing and optimizing for multi-voltage, multi-mode, and multi-corner scenarios.

Multi-Voltage Design: Implementation Architecture
Let’s now look at an ideal multi-voltage MCMM implementation system that includes significant architectural and algorithmic enhancements to the traditional place and route systems. A full multi-voltage physical design flow is shown (Fig. 2).

Multi-voltage setup: The physical design environment for multi-voltage designs needs to be set up accurately and carefully. A little extra time spent in setting up power intent information as expressed in the Unified Power Format (UPF) can pay off by avoiding implementation and verifications problems later in the flow. The UPF file, with the definitions for power domains and the power state table (PST), are fed into the tool database, along with the other library and design data. The PST includes combinations of voltages and power states, which are essentially operational modes in a MCMM environment. Click here to view the code for a basic PST that defines two power states.

You should verify the corners, modes, and power-state setups before continuing through place and route with basic analysis reports (Fig. 3).

Floorplanning and placement: At this early stage in multi-voltage designs, it is important to correctly instantiate the voltage islands and to insert special cells, such as isolation cells, level shifters, power switches, always-on connections, and retention cells. The tool should have a fast, prototyping placer to group cells into partitions and assign partition pins if needed. Power and ground routing algorithms can then create grids for each voltage island. The tool should provide an easy way to analyze the power grids, always-on connections, level shifters, and isolation cells before proceeding with the flow. (Fig. 4).

MCMM Analysis And Optimization
Tools like Mentor’s Olympus-SoC, which performs true MCMM timing and power analysis, can concurrently analyze and optimize across all the modes, corners, and voltage domains for single-pass closure. In related timing analysis reports, voltages should be included as a column along with delay, skew, capacitance, and other data you request. You can then easily see paths crossing from one voltage island to another.

Routing and Optimization: The router should handle all the secondary power connections for retention flops and always-on buffers. It should respect voltage island boundaries, and change routing topology to meet other design constraints (). For example, the router should detour around an island in order to buffer a signal integrity (SI) violation on a non-critical net, but allow critical nets to cross an island. To do this it must receive constant updates on MCMM timing and RC, which it uses to find the optimal solution for meeting power, timing, signal integrity, manufacturability, and area constraints. An advanced router must be DFM-aware so it ‘sees’ and accounts for the manufacturing issues that affect power, especially leakage power, such as variations in on-chip temperature and thickness.

Concurrent MCMM power and timing optimization: Final optimization should be performed concurrently for leakage power, dynamic power, signal integrity, timing, and area. It should also handle situations unique to multi-voltage designs; for example, buffering nets that cross voltage islands. Without concurrent MCMM optimization, the tool may never be able to resolve conflicting needs across different mode/corner/power-state combinations.

The optimizer must also respect isolation cells, level shifters and retention registers, only resizing them with equivalent cells. Likewise, always-on buffers must be respected to avoid breaking connectivity and ending up with the dreaded ‘always-off’ condition.

A final consideration in low power physical design is tool capacity. Designers are often forced to implement their larger designs piece-meal and are never able to see all the information in context at once. This is of particular concern when optimizing for timing and power in a full-chip context, and when you want to consider multiple corners and modes concurrently during clock-tree synthesis and other steps. Physical design tools should be capable of processing 100 million gates or more, hierarchical or flat, so that you can perform full chip-level optimizations without having to use black-box abstractions. In addition to providing better design results, this would also greatly simplify data management and speed up the design turnaround time.

The use of multiple supply voltages is very effective at lowering total power consumption, but this strategy adds several new requirements to physical design flows. Designs with multiple corners and modes that also use a variety of designed-in power reduction strategies require concurrent MCMM timing and optimization to prevent the classic “ping-pong battle” between power and timing closure. Design teams need a place and route system that provides full support for UPF, multi-voltage design styles, and power closure based on MCMM analysis and optimization.

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