Electronic Design

Low-Ripple DAC Implementation

In an example DAC application using Actel’s CorePWM IP DirectCore in low-ripple DAC mode (block diagram, Figure 2, main article), PWM output is averaged to a varying dc voltage. At reset, the PWM duty cycle, or level out value, is 100% and the voltage increases to the rail of 12 V. As the PWM duty-cycle/level-out value changes to 75% and then 50%, the output of the RC filter follows this by dropping to 8 V and subsequently to 6 V. The generated ripple voltage is a function of the RC circuit values, the system clock period, and the PWM duty cycle.

As shown, a field-effect transistor (FET) is used to increase and decouple the output voltage/current from the Fusion device. The load is monitored, and changes to the PWM output are processed via a soft microcontroller. Such MCUs would include Actel’s Core8051 as shown in this design, or alternately any supported embedded processor from simple implementation-specific like Actel’s CoreABC up to the 32-bit ARM CortexM1.

The FET in this design example is used to illustrate the ability to extend the DAC’s output to 12 V. For most applications, 3.3-V native output is sufficient. Higher clock speeds (and therefore lower ripple) can be achieved by driving the RC filter with a general-purpose TTL output.

Low-ripple DAC mode also has the added benefit of requiring a smaller time constant for the filter, which allows for smaller R and C components to be used. Actel offers a low-ripple DAC calculator to assist the designer in determining the ideal values for R and C for a specific application.

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