An “eco mode” method for managing parallel arrays of power modules in an intermediate-bus power-distribution system optimizes efficiency across loads better than conventional approaches commonly used to boost power supply efficiency, such as pulse skipping or the use of low-power “standby supplies.”
The technique is similar to phase shedding, which is often used to optimize light-load performance for multi-phase buck regulators, which are used to provide low-voltage, high-current power to microprocessors. In this case, however, the implementation is different as the “phases” are actually independent power components and the technique is employed at the intermediate bus stage rather than the point of load.
The “eco mode” method makes it possible to eliminate not just the losses in the switching FETs when “phases” are shed, but also the losses in entire modules when the individual components are turned off.
Why Shed Phases?
Regardless of how intermediate buses are implemented, approaches like this are necessary because it has become apparent that high levels of power efficiency are needed across a range of load current demands, and not just at some single target point.
A phase-shedding technique is often employed at the point of load in multi-phase buck regulators and improves the light-load efficiency by turning phases off at light loads. In doing so the power consumption of switching two FETs is saved for every phase that is disabled.
The disadvantage of this approach is that while it works quite well for low-voltage loads, it cannot be extended to high voltages or higher power levels, because the topologies used do not contain parallel power trains that can be enabled and disabled.
Bus converters (BCMs) are isolated fixed ratio dc-dc converters that accept a nominal 48 V input or 384 V input and convert it to standard intermediate bus voltages nominal 12 V or 48 V. They employ a sine amplitude converter topology with zero-voltage/zero current switching that enables extremely high efficiency (typically greater than 95%) as well as power densities that are typically greater than 1000 W/in.3 (see “Sine Amplitude Converters: A New Class Of Topologies For DC-DC Conversion”).
Zeroing In On A Solution
Understanding the design of an intermediate-bus architecture scheme based on sheddable intermediate-bus modules is best understood through a stepwise process. Consider an example with multiple BCMs. The least efficient design approach is one in which the inputs and outputs of each bus converter in an array were connected in parallel for high power application (Fig. 1).
Obviously there would be an advantage to turning off unused BCMs at no-load or lighter load conditions (see “The Economics Of Flattening The Load Curve”). The no-load power dissipation and power loss at light load would be reduced because only one switching power component would be active, so there would be higher efficiency at light load. They would be turned back on to meet higher load demands.
Due to the flexibility of the chips, this concept can be employed in much higher power levels (up to many kilowatts), with higher voltage outputs (up to 55 V dc output).
How can this be accomplished? The “eco mode” technique monitors the input current of each module in a parallel array to turn bus converters off and on as needed (Fig. 2). To achieve this, a current-sense resistor is inserted onto the return leg of the primary side of each bus converter. (The input current of the last bus converter does not need to be monitored but uses a current-sense resistor to balance the voltage drop in the return path of current.)
For an array of three bus converters, two control circuits would be required (Fig. 3). The input of the first control circuit monitors the current passing through the current sense resistor of first bus converter, and it then enables or disables second bus converter in the array based on the input power level of the first bus converter.
The input of the second control circuit monitors the current passing through the current-sense resistor of the second bus converter. Then, it enables or disables the third bus converter in the array based on the input power level of the second bus converter.
To minimize no-load power dissipation and maximize overall efficiency, the control circuits are also designed so they always enable the first bus converter in the array and disable the rest of the bus converters in the array at no load or lighter load.
There is no need for isolation in control circuitry because the control circuitry remains on the primary side of the bus converter array. The bus-converter primary referenced PC-pin voltage powers the control circuit, eliminating the need for an external 5-V source. Power dissipation in each current sense resistor is very low because each resistor senses only a single bus converter’s input current. Control circuitry is also self-monitoring, eliminating the need for other external controllers or monitors.
In the recommended implementation of a control circuit, a 1.25-V voltage reference is generated from the PC voltage of the first BCM. The voltage reference (U1) is connected to the inverting terminal of an operational amplifier for comparison. The REF3312 shown in Figure 4 is a precision low-power-consumption and low-dropout 1.25-V voltage reference, which is available with ±0.2% accuracy. Alternative references can be substituted if higher precision is required.
The first control circuit for eco operation mode senses the input current of the first BCM, turns on the second BCM when the input power of the first BCM reaches more then 250 W, and turns off the second BCM when the input power of the first BCM reaches less than 100 W. The second control circuit is similar to the first but with a different threshold setting. The upper threshold points of the hysteresis circuit are the same, but lower threshold points are different to prevent the false turn-on and turn-off events of bus converters at specific load conditions.
Control Circuit Design
Each control circuit has three blocks (Fig. 4). The gain stage is the voltage amplification stage. Op-amp U2A is configured as a differential amplifier. The current-sense amplifier monitors the input current via the sense resistor. Its voltage drop is low and is not enough to trigger the hysteretic comparator, so the feedback voltage must be amplified. This is achieved by a differential-gain stage using resistors R5, R12, R7, and R10.
Good common-mode rejection and wide common-mode voltage range are important because the amplifier requires large, changing, common-mode signals. The gain value is the same for each control circuit.
In the comparator and hysteresis stage, the output of the amplifier stage is compared to the voltage reference. Op-amp U2B is configured as a comparator with hysteresis. The comparator trips and produces a logic-low to logic-high output transition when the voltage at the non-inverting terminal of the op amp crosses above the reference voltage. This logic-high output can go as high as the positive supply rail of the op amp.
Positive feedback is added around the comparator to generate the hysteresis width (Fig. 5). The comparator trips and produces the logic-high to logic-low output transition when the voltage at the non-inverting terminal of the op amp crosses below the reference voltage. Hysteresis is achieved using resistors R6, R8, and the 1.25-V reference.
The PC logic circuit controls the bus converter’s PC pin, based on comparator output. It has an open-drain output that utilizes the internal pull-up resistor of the PC pin. When the comparator output is in the high state, the voltage on the bus converter’s PC pin floats, and the BCM is enabled. When the comparator output is in the low state, the voltage on the bus converter’s PC pin is pulled low and the BCM is disabled.
This circuit is designed using MOSFETs Q1, resistors R4 and R9, and capacitor C10 to generate delay on the falling edge of load. It is necessary to have a proper separation in delay for each control circuit to prevent overlap events of BCMs turn-off when load decreases. This circuit should also be designed while keeping the maximum toggle rate of PC in consideration.
For three bus converters (stepping down 384 V to 12 V), light-load efficiency is 7% higher at a 90-W load in eco mode than in simple mode and it is 3% higher at a 200-W load (Fig. 6). No-load power dissipation is 18 W and 7.4 W for an array of three in simple mode and eco mode, respectively. Therefore, the no-load power dissipation is 10.6 W lower for an array of three using this technique.
The no-load power dissipation for a parallel array of four bus converters (384 V to 12 V) is 24 W and 8 W in simple mode and eco mode, respectively. Light-load efficiency is more than 10% higher at a 90-W load and more than 5% higher at a 200-W load for an array of four in eco mode. From this it is apparent that the light-load efficiency margin is increased further as the number of bus converters in the array are increased (Fig. 7).
Figure 8a shows the output current of each BCM for the presented eco mode technique for the rising edge of a load step. Figure 8b shows the output current of each BCM for the presented eco mode technique for the falling edge of a load step.
Beyond these steps to optimize the real-time efficiency, the designer must look closely at power-component and control-circuit design. There are inherent delays in power components and control circuits, and so the first BCM in the system must maintain its output voltage before the control circuitry turns on the unused BCM during the fast load step transient—the system should be able to handle full power for a short time.
The power system designer should also consider the maximum slew rate of the load and its repetition rate. These functions require smart management from control circuits. Facilitating this, digital power-management control circuits can automatically detect the load condition and smoothly switch to the appropriate converter.
This version of eco mode operation is limited to six bus converters in the parallel array. Alternative implementations could be used to increase that number. For example, at no load or light load, one might turn on only one BCM (Fig. 9). In this case, Rsense1, Rsense2, and Rsense3 are all current-sense resistors. Rsense2 and Rsense3 are added to balance the voltage drop in the input current return path to improve the current sharing when all bus converters are turned on.
Minimizing the no-load power dissipation and maximizing light-load efficiency saves money by minimizing the energy used by the load. In the kind of high-power arrays discussed in this article, this functionality can be achieved by turning unused bus converters off at light loads to minimize the power dissipation of the bus converter array. Unused bus converters are then turned on based on load demand to maximize the light-load efficiency for a given load profile.
To understand the value of this approach, consider the power usage of a data center with 100 Web front-end servers, 100 application servers, 100 database servers, and 100 backup servers. Assume that each server runs for eight hours each day at idle power usage, eight hours at average load, and eight hours at peak load, using six 384-V to 48-V BCM converters per server. Then assume that the cooling system efficiency is 50%.
A data center using the kind of power distribution described in the article will further save 32.5 W per server at idle power usage and 19.5 W at average load. Assuming $0.10 per kWh, the total savings could then be about $12,000 per year.