Demands for rich, diverse, and instantaneous networked multimedia experiences from mobile consumer devices such as smart phones, tablets, and ultrabooks continue to re-sculpt the industry’s landscape. Nearly every area of system design is feeling the impact, from the screen and peripherals such as radios, cameras, and data interfaces to the application processor. These changes, in turn, significantly affect the implementation of the power-management functions needed to control the delivery of power throughout the system and optimise efficiency for maximum battery life.
Today’s most popular mobiles, for example, feature multiple cameras, including front- and rear-facing cameras. Some include support for 3D photography and video, with resolution reaching 41 Mpixels in certain cases. To create even more engaging viewing experiences, there’s now a trend toward larger screen sizes that feature capacitive multi-touch capability, as well as the implementation of 3D screens on the most advanced models.
As for wireless connectivity, the advent of mobile payments using near-field communications (NFC) adds demand for greater RF connectivity in addition to GSM, Bluetooth, Wi-Fi, and GPS. Users of tablets and smart phones also expect high-quality end-to-end speech with louder, better-quality speakerphone performance, high-quality microphones, and high-definition audio playback. Moreover, the popularity of apps such as social networking and mobile Web access means that users crave ever-more data bandwidth through 3G connections and 4G LTE.
Essential to any mobile device are its internal application processors. They have moved from the single-core devices considered adequate just a couple of years ago to dual-core and now quad-core implementations to handle the increasingly diverse and high-performance functionality available. The latest families of multicore application processors also integrate extra peripherals, such as the DRAM controller and a media/graphics co-processor (e.g., the ARM Neon).
As a result, power-management functions must be complex enough to handle the increasing number of peripherals and processor cores populating today’s mobile platforms. Power management must also deal with more complex charging scenarios, as today’s users are as apt to charge their devices from sources like a PC USB port or car charger as a conventional mains-powered charger.
Impact Of Multicore Processors
Various smart-phone subsystems connect to a system’s power-management scheme (Fig. 1). To supply these subsystems, the power-management IC (PMIC) must implement sufficient buck or boost converters and low-dropout (LDO) regulators. Furthermore, it has to take responsibility for aspects such as power-up and power-down sequencing and high-accuracy fuel gauging to provide a reasonable assessment of remaining battery life.
Power-up and power-down control is particularly important for the application processor since multiple cores have critical timing dependencies. Intelligent power management also must handle the increasing numbers of sensors supporting functions such as backlight dimming, camera gesture recognition, navigation, and proximity detection.
As processor architectures evolve from single- to dual-core architectures, power-management designs tend to continue supplying both cores as a single power domain. With quad-core processors, separating each processor into its own power domain (supplied by individual regulators) gives system designers greater flexibility to control the power to each core. It’s possible to power-down cores individually and size each regulator to supply a lower worst-case current demand.
De-integrating Power Management
The deep nanometre process nodes of multicore application processors are having a profound impact on power-management implementation. In older platforms like 2G phones, the baseband, application processor, and PMIC were usually integrated into one chip. This is no longer possible with application processors fabricated in deep nanometre nodes, because shrinking feature sizes demand lower operating voltages.
For CMOS chips, of course, shrinking feature size will reduce the maximum voltage that can be applied. Figure 2 shows the reduction in core and I/O voltages with process geometry and compares these voltages with maximum battery voltage.
The PMIC requires a direct connection to the battery voltage (a one-cell Li-ion battery up to 4.5 V), and therefore can’t be fabricated in the 40-nm, 32-nm, and 28-nm nodes used by popular quad-core ARM Cortex-A9 application processors. Hence, the PMIC functionality must de-integrate from the application processor. Today’s 3G handsets embody this trend, typically having a discrete application processor with external PMIC working alongside a baseband processor with integrated power management.
In some applications, it’s sensible to integrate the PMIC with an audio subsystem IC comprising the DSP, codecs, and functions such as class-D speaker amplifiers and class-G headphone amplifiers. Dialog Semiconductors’ DA9059 is an example of a combined PMIC and audio subsystem IC for mobile applications that can save approximately 43% on bill of materials (BOM).
Looking further ahead, it’s expected that 4G architectures will incorporate two complex PMICs serving the baseband and the application processor individually.
A de-integrated system power-management solution can be achieved using discrete components. Application processor vendors have proposed reference designs consisting of as many as six individual ICs.
In contrast, single-chip PMICs integrate all of the required buck converters for core, I/O, and memory supply voltages; LDO regulators for peripherals; battery charging; and control intelligence (Fig. 3). This not only enables designers to reduce the BOM, it also enhances overall efficiency, too, extending battery life. Some PMICs support dynamic voltage scaling in one or more power domains as well, which helps optimise processor energy per task, leading to higher efficiency.
BOM Reduction And Power-Domain Flexibility
Single-chip external PMICs, when compared to similar discrete solutions, have demonstrated lower buck quiescent current and lower LDO voltage, leading to improved efficiency and lower internal power dissipation. Power dissipated during battery charging has an even greater bearing on system thermal management. A PMIC with a switching battery charger and intelligence to track the battery charge can reduce internal power dissipation by more than 80% for a 1.3-A/5-V charger, significantly decreasing heat build-up within the enclosure.
The latest generations of external PMICs integrate power-management functionality on-chip. It thus offloads the application processor from system supervisory tasks such as on/off control, power-up, and power-down sequencing—tasks traditionally handled in software. This helps optimise power management that, in turn, boosts energy efficiency. Moreover, it enables power up and power down without intervention from the application processor.
A graphical tool like the Dialog Power Commander can be used to configure PMIC supervisory tasks. Engineers can select output voltages and currents for individual dc-dc buck converters and LDOs, select operating modes for best efficiency or lowest noise, and optimise power-up and power-down sequences via simple drag-and-drop. When complete, the saved configuration can be programmed into the integrated OTP for development or high-volume production purposes. In addition, the configuration is easily modifiable if required.
Success in today’s mobile markets depends heavily on delivering the right performance and functionality at a competitive price, within an acceptable time-to-revenue window. As high-performance, multicore deep nanometre application processors force important power-management functions off-chip, integrated PMICs help to meet these targets by simplifying design, reducing BOM, and extending battery life.