With this circuit, which adds a power-down function to analog I/O ports (for example, the AD7769 and AD7774), the operating time of battery-powered equipment can be extended. Moreover, the diodes ordinarily needed to protect the devices against power-supply missequencing can be eliminated (see the figure).
In the circuit, MOSFETs Q1 and Q2 switch the +5- and +12-V supplies, respectively, in a sequence controlled by two cross-coupled CD4001 CMOS NOR gates (U1C and U1D). The sequence in which power is applied is important: The controlled circuits may be damaged anytime VCC exceeds VDD + 0.3 V. Consequently, the NOR gates must be powered from a 12-V supply throughout the power-down sequence.
Bringing the Power Down control high (+5 V) applies power to the controlled circuit by turning on both MOSFETs. Specifically, raising Power Down brings the output of U1C low, causing capacitor C1 to discharge VOL exponentially with time constant R1C1. As C1C falls, two events occur. First, it puts a negative gate-source voltage on p-channel Q1, turning it on.
Second, it causes output gate U1D to go high. With the output of U1D high, capacitor C2 charges exponentially to VOH—about 12 V—applying a positive gate-source voltage to turn on Q .
In the power-down mode, the Power Down control is brought low and the RC circuits and their delays work in reverse. Consequently, capacitor C2 discharges to the logic input of U1C before C1 can charge. Hence, Q2 turns off before Q1.