By coupling a new chip-integration flow with the latest release of its Virtuoso chip editing tool, Cadence will enable designers to perform full-scale physical IC integration across multiple design domains. These domains include analog, custom digital, RF, memories/arrays, and digital standard cells.
The integration flow and Virtuoso chip editor give designers an integrated physical design suite, from floorplanning through chip finishing and tapeout. It offers a seamless, bidirectional path to and from Cadence's Encounter digital IC design platform through the OpenAccess database. This ensures interoperability between custom and digital design environments.
Cadence's new version of the Virtuoso chip editor, Version 3.3, offers immediate visual feedback on design rule violations and quicker chip finishing, thanks to its ability to alert users to accidental opens and shorts in connective paths. A "meet in the middle" approach combines the speed of top-down design with the silicon precision of bottom-up design. The flow can bidirectionally pass data between multiple design domains. It offers floorplanning capabilities and analog routing.
The new chip integration flow and Virtuoso Chip Editor are available now. Pricing for a one-year Virtuoso license starts at $40,000.
Cadence Design Systems