EE Product News

Design Application Adds Crosstalk Delay Analysis

Version 1.2 of Dolphin physical design system targets users of 0.18 µm, and below, technology. The tool can calculate path delays induced by crosstalk interactions on interconnects that are in close proximity on a chip. New timing analysis technology allows analysis of multiple aggressors for a victim net and produces an accurate timing result for the best and worst case timing paths. The software allows users to achieve design closure in one pass as the tool optimizes for all design constraints simultaneously. Other improvements include clock tree synthesis and logic optimization as well as compatibility with more third party tools through standards such as SDF, SPEF and GDS II. Starting price is $420,000 for a single CPU perpetual license.

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