Electronic Design

Design Verification Environment Packed With Four Key Tools

Verification Navigator is an integrated design verification environment that provides code coverage, test-suite verification, state-machine coverage, and circuitry analysis for Verilog, VHDL, and dual-language designs. Its structured verification methodology supplies information designers need, including how well their test benches verify each block in the design, and where they should focus additional verification efforts. Based on HDLCover, VeriSure, and VHDLCover code coverage tools, the navigator also lets designers perform multiple verification tasks from a common, easy-to-use interface.

Four tools are included with the device. The VN-Cover, a single-kernel, dual-language, simulator-independent code-coverage tool, allows code coverage to be generated from a single simulator run on dual-language simulators. A test-suite optimization tool called VN-Optimize sorts test sets, enabling the most productive tests to be run first.

VN-State automatically extracts an FSM diagram from the HDL code and calculates the transition coverage metrics of the state machine based on simulation results. Finally, the VN-Activity tool can be used for circuit-activity analysis.

The Verification Navigator's list price starts at $20,000.

TransEDA, 985 University Dr., Los Gatos, CA 95032; (408) 907-2000; fax (408) 907-2085; www.transeda.com.

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