EE Product News

Design Verification Tool Uses Novel approach

Said to increase the capacity and speed of formal verification for the largest system-on-chip (SoC) designs, Design VERIFYer 2001.2 incorporates a top-down approach (TDA) capability that conducts automatic module-by-module compilation and comparison of hierarchical designs. For designs with modules of 250,000 gates or more, the TDA is said to significantly increase verification speed. The new release also provides a push-button interface to Apollo-II that is said to allow easy verification of design changes such as clock-tree synthesis, scan insertion, logic optimization, and ECOs. The verification tool supports all major computing platforms and is now available under Linux 2.2x. For more details, call AVANT! CORP., Fremont, CA. (510) 413-8000.

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