EDA Breaking News: PSL/Sugar Support

Feb. 16, 2004

Support for Accellera's PSL/Sugar and for assertion-based verification in general has been added to Verific Design Automation's Verilog and VHDL front-end software products. All of Verific's HDL component software packages, which now include a PSL/Sugar reader, will enable assertion-based verification. Moreover, Verific recently joined the PSL/Sugar Consortium. PSL/Sugar is a powerful, concise language for assertion specification and complex modeling. Visit www.verific.com and www.pslsugar.org.

About the Author

David Maliniak

MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.