Support for Accellera's PSL/Sugar and for assertion-based verification in general has been added to Verific Design Automation's Verilog and VHDL front-end software products. All of Verific's HDL component software packages, which now include a PSL/Sugar reader, will enable assertion-based verification. Moreover, Verific recently joined the PSL/Sugar Consortium. PSL/Sugar is a powerful, concise language for assertion specification and complex modeling. Visit www.verific.com and www.pslsugar.org.