Electronic Design

Formal Verification Tool Targets Multimillion-Gate SoC Designs

The Formality 1999.10 is a formal verification tool for equivalency checking of multimillion-gate system-on-a-chip (SoC) designs. It comes with an all-new, totally independent Verilog HDL front end that provides a fivefold speed improvement in HDL read time, along with support for encrypted DesignWare models and new language constructs. This tool also features a 40% reduction in memory utilization, enabling increased design capacity. Native support for Verilog simulation libraries, in addition to the existing support for the company's libraries, is included. It reads and interprets the company's simulation libraries at runtime, providing much faster setup and broader support of user-defined primitive (UDP) styles. Now available, current Formality customers with maintenance contracts will receive new software and keys at no extra charge.

Synopsys Inc., 700 East Middlefield Rd., Mountain View, CA 94043; (650) 584-5000; www.synopsys.com.

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