HDL Environment Adds Direct Compile Verilog Simulator

The Active-HDL design environment now includes Active-HDL/VLOG, a stand-alone, IEEE 1364-95 Verilog-compliant simulator. The new Verilog simulation kernel includes Verilog design entry, test-bench generation, and direct-compile Verilog simulation.
The application also offers complete OVI compliance, PLL support, and what is claimed to be seamless integration between design entry and simulation-debugging software. Other features include state machine and block-diagram editors, automatic test-bench generation, graphical-data flow, advanced Verilog debugging and adjustable simulation resolution, EDIF netlist simulation, TCL/TK scripting, timing simulation, and EDIF netlist simulation. Pricing starts at $5,200.