Electronic Design

<i>Step-By-Step Functional Verification With SystemVerilog And OVM </i>

By Dr. Sasan Iman

The industry’s first book covering the Open Verification Methodology (OVM), titled “Step-by-Step Functional Verification with SystemVerilog and OVM,” provides a complete reference to adopting the OVM for functional verification. Written by Dr. Sasan Iman, a principal with SiMantis Inc., the book is being promoted by Cadence and Mentor on the OVM World Web site (www.ovmworld.org) to help the OVM community better understand and use the popular methodology.

In addition to providing methodological guidelines, Iman’s book helps users learn the SystemVerilog language, and covers use of SystemVerilog and the OVM library for building a verification environment for a realistic design example. It packs more than 500 pages of original technical content, none of which duplicates the documentation already available on OVM World.

The Open Verification Methodology, based on the IEEE 1800-2005 SystemVerilog standard, is the first open, language-interoperable, SystemVerilog verification methodology in the industry. It provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows.

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