A joint electronic system-level (ESL) design flow forged by CoWare and Sonics has been upgraded to its second-generation incarnation. The flow, which combines Sonics’ system-level interconnect IP technology with CoWare’s virtual platform technology, gives designers advanced debugging and analysis capabilities for platform architecture design and platform verification.
Semiconductor companies are faced with new design challenges caused by the transition from single application systems to multi-application systems. In particular, local memory subsystems are replaced with complex memory hierarchies; local, shared buses are replaced with intelligent interconnects (NoCs); and single-processor IP is replaced by multiple processors and interconnect IP. The collaboration between Sonics and CoWare addresses this growing trend by enabling the intelligent interconnect and complex memory modeling capabilities accessible through the SonicsStudio development environment to seamlessly interoperate with the system modeling capabilities of CoWare Platform Architect.
TLM platform capture and analysis can now be executed by utilizing the SonicsStudio development environment for managing the detailed configuration of the Sonics models and through direct links with CoWare Platform Architect, include multiple processor models and other IP to perform system level capture and analysis using CoWare Platform Architect.
The CoWare-Sonics joint flow uses CoWare’s Platform Architect and SonicsStudio to create platform models based on Sonics SMART Interconnect IP. The integration implementation has been driven by customer design requirements. It addresses the needs of architects that want to explore and optimize the highly-configurable interconnect and memory sub-system solutions offered by Sonics.
CoWare Platform Architect is used to create and configure the platform, resulting in the ability to get a high-level overview of the entire platform which helps ease architecture decisions. SonicsStudio is used to configure the extensive set of Sonics IP parameters, which results in consistency checking that eases Sonics IP optimization. The flow provides advanced SystemC debug features enabling designers to reach product goals quicker. Additionally, Sonics’s SonicsMX and Sonics MemMax tools provide analysis for rapid interconnect architecture optimization and QoS optimization.
The Sonics-CoWare ESL2.0 solution for Sonics SMART Interconnects is available now from CoWare. As part of this solution, CoWare distributes an ESL version of SonicsStudio. To create Verilog RTL, the configuration data developed in the ESL 2.0 CoWare Platform Architect/SonicsStudio environment can be reused in the SonicsStudio version available from Sonics.
Contact CoWare and Sonics directly for pricing and delivery information.