The purpose of fill synthesis is to meet foundry CMP design rules by inserting dummy shapes on the metal, via, active, and poly layers of an IC design. These CMP rules enable the foundry to maintain a planar wafer surface during fabrication. The complexity of the fill-related design rules has increased with each advance in process node. As a result, the existing fill methodology is under significant strain.
Typically, tools originally intended for design-rule checking (DRC) perform fill synthesis. Engineers have been able to create clever scripts using basic geometry commands to insert design rule-compliant fill shapes into their designs. Although the DRC tool providers have done a good job of providing extra functionality to support this usage of their tools, the fact is that these fill-insertion scripts have grown to become overwhelmingly complex over time.
Some new rules are particularly challenging. For example, almost all 65-nm design-rule manuals include the requirement to maximize smoothness rather than simply maintain density within preset bounds. Another challenging requirement is the consideration of the wafer topography impact of the entire metal stack, rather than just a single layer at a time, as has been done until now. There is also a requirement to consider pattern density control at different length scales (i.e., with respect to different window sizes). More advanced requirements include designing fill to control the pattern environment for lithography and etch, to have symmetric RC impact on matched structures in analog circuitry, and to correctly handle hard IP integration.
One important issue that a future fill solution must address is the impact of the fill shapes on circuit timing and power. To this end, some are looking to detailed routers to provide a fill solution that doesn't harm timing. However, a router has as its primary task the routing of wires within a timing budget, which is a complex problem by itself. Overloading a router with additional rules is not the best way to achieve convergence, nor do routers typically have the global view of a chip needed to ensure high-quality smoothness results.
Although foundry fill requirements have thus far been captured in design rules, design rule complexity is reaching practical limits. For the future, we need an alternative approach. Already, foundries are cooperating with DFM tool providers to enable an alternative to spiraling design rule complexity; foundries will provide CMP models that can predict 3D wafer topography given a particular layout topology. Fill tools will be required to use these CMP models to drive their decisions, leading to fill solutions that meet the foundries' planarity requirements.
The current solution to fill synthesis has been pieced together on top of tools that were not designed to handle it. It is time to consider a fresh approach, designed from the start with the goal of optimizing wafer planarity and use of the design's variability budget, without harming chip timing or power.
With design-rule complexity increasing with addition of recommended design rules, it will be difficult for the conventional fill synthesis paradigms to cope. New manufacturing and variability control requirements are driving the creation of more sophisticated fill solutions. New fill tools must be model-based. They must work to minimize density gradient. They must minimize the impact of fill insertion on timing and signal integrity, and they must help to enhance a chip's process and operational latitudes. In summary, a dedicated, intelligent fill synthesis tool is an essential component in an electrical DFM toolkit that provides the best possible process and performance latitude for a design.