EE Product News

Methodology Addresses Analog And Mixed-Signal Design

product pic

Using a top-down design/verification methodology for analog or mixed-signal system-on-chip (SOC) designs, the AMS designer contains a single-engine, mixed-signal simulator that can simulate standard netlist formats. Designs may be constructed and simulated using any combination of Verilog, Verilog-A, Verilog AMS, Spectre, SPICE, SpectreHDL, and VHDL.
The simulator also provides debugging and simulation control using the SimVision environment. It also supports cross-probing between waveforms and schematics and the ability to traverse a design's hierachy synchronously. A waveform viewer allows analog and digital wave forms to be viewed simultaneously. Available in the fourth quarter of 2000, pricing starts at $68,000 for a one-year license.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.