Power-saver kit targets all designers

Bracknell, England: Employing advanced low-power techniques in your next design is within the reach of engineers of all different experience levels. Cadence Design Systems' Low-Power Methodology Kit, a complement to the company's Low-Power Solution, provides a working end-to-end methodology that covers aspects of logic design, functional verification, and implementation.

Example IP, scripts, and libraries come with the kit. Design teams without extensive low-power implementations can thus quickly optimise their lowpower design environment and accelerate their time to lowerpower, more competitive systemon- a-chip products.

It provides a generic wireless application design, implemented using multi-supply voltage and power shut-off methods, and all associated command scripts and technology files needed to carry the design through the entire end-to-end flow. The example IP in the design is from Cadence; third-party contributions include ARM processor and AMBA onchip communication technology, Wi-Fi from Wipro, USB 2.0 from ChipIdea, 65nm ultra-low-power memories from Virage Logic, and 65nm technology libraries from TSMC.

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