Electronic Design

Tool Set Gives Designers High-Performance Results

A complete set of design tools lets designers conduct optimization at the gate, transistor, and polygon levels, thereby meeting stringent area and performance needs.

The Tempest-CELL, an automatic cell-layout development tool, generates high-speed, handcrafted density, silicon-process-independent cell libraries. Optimized for static CMOS technologies, it offers handcrafted design density and an increase in orders of magnitude in layout design productivity. The Tempest-DYNACELL, a tool for automated generation of dynamic logic cells, augments the Tempest-CELL for dynamic logic generation.

Tempest-BLOCK is an automated hierarchical physical design tool that offers the same layout density of handcrafted designs. Its parasitic-driven design methodology features RoPRo architecture. This, as a result, ensures high performance, proprietary optimization algorithms, fully automated block layout, and interactive incremental design capabilities.

All of these products feature process portable design, optimized across a range of very deep submicron (VDSM) technologies. They also run on Sun Solaris and HP UX platforms. Available now, pricing starts at $200,000.

Syncon Design, 1309 S. Mary Ave., Sunnyvale, CA 94087; (408) 962-3300; fax (408) 530-0933; www.syncon-design.com.

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish