Electronic Design

“Turbo” Technology Enhances RF Verification

In an effort to address the challenges of verifying wireless ICs implemented in advanced CMOS processes, Cadence has added the "turbo" technology it recently brought to the Virtuoso Spectre Circuit Simulator to its RF analysis capabilities. The claimed result is performance improvements of two- to five-times, and sometimes more, for analysis and verification of large RF circuits targeting advanced CMOS process nodes, and with no degradation in accuracy.

This “turbo” technology complements a complete manufacturability-aware suite of tools for the design, implementation and verification of RFICs. Based on the Virtuoso custom design platform, these tools enable designers to deal with the challenge of integrating RF with analog/mixed-signal baseband, and the emerging need for RFIC-focused electromagnetic analysis. It improves time to market and overall design costs through faster and more accurate verification that reduces design turnaround time and expensive silicon respins.

The suite includes the Cadence Virtuoso RF Designer, which brings a full-wave fast planar electromagnetic (EM) field solver to the RF/wireless designer's desktop. Virtuoso RF Designer offers designers advanced verification capabilities for faster electromagnetic analysis of complex structures and geometries. Virtuoso RF Designer integrates seamlessly into the Virtuoso front-end and makes use of Cadence's electromagnetic analysis technology to accelerate and accommodate large designs found in today's RFICs and systems-on-a-chip (SoCs). The Cadence RFIC suite also provides an interactive link between system design and circuit design by integrating with Simulink from The MathWorks. RF system designers use MATLAB and Simulink for system design and refining specifications for each RF block in the context of the system. Thanks to the integration between Virtuoso’s multi-mode simulation and MATLAB and Simulink, RFIC designers can insert their block schematics and post-layout netlist directly in the system-level block diagram and use co-simulation to verify that the implementation meets system-level specifications.

In addition, Cadence has developed a toolbox for MATLAB that allows designers to access their simulation results in MATLAB for advanced visualization and post-processing.

For pricing and delivery information on Cadence’s RF design and verification tools, contact Cadence directly.

Cadence Design Systems
www.cadence.com

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