To be implemented in SOCs used in wireless applications, a family of IP cores is said to use 80% less SRAM than comparable designs. The offering includes a turbo encoder, a turbo decoder, and a full-duplex turbo codec that combines encoding and decoding. All three are available in synthesizable VHDL or Verilog and come with cycle- and bit-accurate ANSI C++ or SystemC models for SoC-level verification. HDL versions of the turbo encoder take 22,890 gates, employ 1 KB of single-port SRAM, and have a maximum system clock of 200 MHz. The HDL versions of the turbo decoder take 45,300 gates, use 6.3 KB of SRAM, and have a maximum clock speed of 150 MHz. The turbo codec with encoder and decoder uses 45,600 gates, uses 6.3 KB of SRAM, and has a maximum clock speed of 150 MHz. Prices start at $70,000. ADELANTE TECHNOLOGIES, Leuven, Belgium. +32 16 39 14 11.