Ultra-High-Density Cell Library Shrinks Area, Power Usage

Aug. 4, 2003

Through use of an ultra-high-density standard-cell library added to the ASAP Logic family, designers can achieve up to 30% improvements in logic-block area usage while typically consuming up to 20% less power than conventional architectures. The smaller, more routable cells leverage lower device capacitance and shorter wire lengths to achieve the power-consumption gains. Prices start at $25,000.

Virage Logic Corp.www.viragelogic.com

About the Author

David Maliniak

MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.